I got some info regarding the switching problem ( to 48 MHz), not fully sure but it's likely true, In short: Instability issues for 192 MHz and 240 MHz presets are because **we are still in SDR50 Mode not SDR104,
After the switch to 48 MHz I was Unable to apply the overclock again even after un-patching the memory and re-enabling the overclocking task, it stuck on 21MB/s
By changing 4 to 3 in this line:
if (sd_setup_mode_enable && regs[sd_setup_mode_reg] == 4) /* SDR50? */
to if (sd_setup_mode_enable && regs[sd_setup_mode_reg] == 3) /* SDR50? */
And enabling un-patch memory for clearing previous overclock, and re-overclocking by the change above, now I can get ~41 MB/s without restarting the camera and after it switched to 48 MHz
I set the registers values to the default ones from Canon which are:
static uint32_t sdr50_700D[] = { 0x3, 0x3, 0x4, 0x1D000301, 0x0, 0x201, 0x201, 0x100, 0x4, 0 };
I re-overclocked it a to 120 MHz or 132 MHz (the one below 160 MHz) and it gave 53 MB/s write speed in play mode, these are the settings:
static uint32_t sdr50_700D[] = { 0x3, 0x3, 0x3, 0x1D000301, 0x0, 0x201, 0x201, 0x100, 0x3, 0 };
Overclocking more than that is not possible, gives Card full error, and in benchmark gives ~4657 MB/s in read/write , these values appears in benchmark when the Card full error is presented and when you can't read on write on the card,
So if it was this SDR50, [sd_setup_mode_reg] == 4) /* SDR50? */
then is't this SDR25 ? [sd_setup_mode_reg] == 3)
And if this code able to bring SDR104:
static void sd_set_function_log(uint32_t* regs, uint32_t* stack, uint32_t pc)
{
qprintf("sd_set_function(0x%x)\n", regs[0]);
/* UHS-I SDR50? */
// if (regs[0] == 0xff0002)
// {
regs[0] = 0xff0003;
// }
..
..
patch_hook_function(sd_set_function, MEM(sd_set_function), sd_set_function_log, "SDR104");
Why it can't bring SDR25 which will not accept a preset above 132 MHz ?
Maybe it could accept 160 MHz preset and that happen when I brought SDR104 peace of code again to the code but with some changes:
static void sd_set_function_log(uint32_t* regs, uint32_t* stack, uint32_t pc)
{
qprintf("sd_set_function(0x%x)\n", regs[0]);
/* UHS-I SDR50? */
// if (regs[0] == 0xff0002)
// {
regs[0] = 0xff0004; /*now it's 0xff0004 instead of 0xff0003*/
// }
..
..
patch_hook_function(sd_set_function, MEM(sd_set_function), sd_set_function_log, "SDR104");
And I applied 160 MHz preset (after the swtich) which is:
static uint32_t sdr50_700D[] = { 0x3, 0x3, 0x2, 0x1D000201, 0x0, 0x201, 0x201, 0x100, 0x2, 0 };
Now it accepted preset more than 132 MHz, and I got 62 MB/s Write Speed, but not constant it gives Card full error after some seconds . .
Conclusion
I don't think SDR104 patch is an SDR104 patch
**Aren't we already in SDR104 by default ? and maybe the switch to 48 MHz mode is the SDR50 mode (according to SD Association and all the internet, max speed @ SDR104 is 104 MB/s , and SDR50 @ 50 MB/s so my results above because it switched to SDR50 not SDR25, and this make a lot of sense in the results above, and in the previous results I always commented out SDR104 patch, and I always got 160 MHz , 192 MHz, 240 MHz working fine, and with the patch enabled I had no difference in speed at all, so as a1ex said it's need some tuning to avoid random errors)
Card full error happens when you apply high frequency preset in not supported mode like SDR25, and SDR25 can't switch to 48 MHz because it is 48 MHz already so it gives Card full error
You can make a change from:
if (sd_setup_mode_enable && regs[sd_setup_mode_reg] == 4) /* SDR50? */
to
if (sd_setup_mode_enable) /* SDR50? */
This will apply any given registers values in any mode and the registers values will not change after the switch or sdSoftReset, so now instead of 21 MB/s speed when it switch to 48 MHz mode, it will give Card full error, now we know how to lock the values . . but how lock SDR50 or SD104 mode ?
I am not saying my assumptions are all true, but we are missing something . . maybe.