I have found some debug function which prints the whole interrupt vector table of the RPs ICU to UART (firmware version 1.6.0):
0xe0136920: void printInterruptVectorTable(void)
It produces the following output:
<=-=-=- Vector Start -=-=-=>
0,-noise-
1,EDOMAIN_OPERA_OPEKICK0
2,EDOMAIN_EDMAC_5_WR_S1
3,EDOMAIN_EDMAC_1_RD_L0
4,EDOMAIN_VITON
5,EDOMAIN_OPERA0
6,SYNC_irq_intb60v
7,SYNC_vi_out7
8,TMU_int_SWA
9,TMU_int_pulc
10,INTC_XINT *IRQEXT
11,TCU_T0OUT *IRQEXT
12,postman_RCVINT0
13,postman_FIFOINT0
14,Eeko_TIMER_OC0_INT*ASYMMETRIC
15,Eeko_TIMER_IC0_INT*ASYMMETRIC
16,EDOMAIN_SYNGEN_1
17,EDOMAIN_OPERA_OPEKICK1
18,EDOMAIN_EDMAC_6_WR_S0
19,EDOMAIN_EDMAC_1_RD_M0
20,EDOMAIN_AFFINE
21,EDOMAIN_OPERA_ERR0
22,SYNC_irq_intb59v
23,SYNC_vi_out8
24,TMU_int_SWB
25,TMU_int_occh0SP
26,INTC_XINT *IRQEXT
27,TCU_T1OUT *IRQEXT
28,postman_RCVINT1
29,postman_FIFOINT1
30,Eeko_TIMER_OC1_INT*ASYMMETRIC
31,Eeko_TIMER_IC1_INT*ASYMMETRIC
32,EDOMAIN_SYNGEN_2
33,EDOMAIN_OPERA_OPEKICK2
34,EDOMAIN_EDMAC_6_WR_SS0
35,EDOMAIN_EDMAC_1_RD_S0
36,EDOMAIN_AFFINE_OVR_ERR
37,EDOMAIN_OPERA_ABORT0
38,SYNC_irq_intb50v
39,SYNC_vi_out9
40,TMU_int_ocall
41,TMU_int_occh0EP
42,INTC_XINT *IRQEXT
43,TCU_T2OUT *IRQEXT
44,postman_RCVINT2
45,postman_FIFOINT2
46,Eeko_TIMER_OC2_INT*ASYMMETRIC
47,Eeko_TIMER_IC2_INT*ASYMMETRIC
48,EDOMAIN_SYNGEN_3
49,EDOMAIN_OPERA_OPEKICK3
50,EDOMAIN_EDMAC_6_WR_SS1
51,EDOMAIN_EDMAC_1_RD_S1
52,EDOMAIN_SARIDON
53,EDOMAIN_OPERA1
54,SYNC_irq_intb49v
55,SYNC_vi_out10
56,TMU_int_pulgenCEI
57,TMU_int_occh1SP
58,INTC_XINT *IRQEXT
59,TCU_T3OUT *IRQEXT
60,postman_RCVINT3
61,postman_FIFOINT3
62,Eeko_TIMER_OC3_INT*ASYMMETRIC
63,Eeko_TIMER_IC3_INT*ASYMMETRIC
64,EDOMAIN_SYNGEN_4
65,EDOMAIN_OPERA_OPEKICK4
66,EDOMAIN_EDMAC_6_WR_SS2
67,EDOMAIN_EDMAC_1_RD_SS0
68,EDOMAIN_KURABO
69,EDOMAIN_OPERA_ERR1
70,SYNC_irq_intl60v
71,SYNC_vi_out11
72,TMU_int_icapCE1
73,TMU_int_occh1EP
74,INTC_XINT *IRQEXT
75,TCU_T4OUT *IRQEXT
76,postman_RCVINT4
77,postman_FIFOINT4
78,Eeko_TIMER_OC4_INT*ASYMMETRIC
79,Eeko_TIMER_IC4_INT*ASYMMETRIC
80,EDOMAIN_SYNGEN_STP
81,EDOMAIN_OPERA_OPEKICK5
82,EDOMAIN_EDMAC_6_WR_SS3
83,EDOMAIN_EDMAC_1_RD_SS1
84,EDOMAIN_MESSI
85,EDOMAIN_OPERA_ABORT1
86,SYNC_irq_intl60v_st1
87,SYNC_irq_intvi4
88,TMU_pulc_ch0
89,TMU_int_occh2SP
90,INTC_XINT *IRQEXT
91,TCU_T5OUT *IRQEXT
92,postman_RCVINT5
93,postman_FIFOINT5
94,Eeko_TIMER_OC5_INT*ASYMMETRIC
95,Eeko_TIMER_IC5_INT*ASYMMETRIC
96,EDOMAIN_SYNGEN_FRM
97,EDOMAIN_OPERA_OPEKICK6
98,EDOMAIN_EDMAC_6_WR_SS4
99,EDOMAIN_EDMAC_1_RD_SS2
100,EDOMAIN_DANCING_FEN
101,EDOMAIN_HAIDI_PNL_WR
102,SYNC_irq_intl59v
103,SYNC_irq_vi4_set_1
104,TMU_pulc_ch1
105,TMU_int_occh2EP
106,INTC_XINT *IRQEXT
107,TCU_IPCOUT4
108,postman_RCVINT6
109,postman_FIFOINT6
110,Eeko_TIMER_OC6_INT*ASYMMETRIC
111,Eeko_TIMER_IC6_INT*ASYMMETRIC
112,EDOMAIN_SYNGEN_1_A
113,EDOMAIN_EDMAC_1_WR_L0
114,EDOMAIN_EDMAC_DAN_WR
115,EDOMAIN_EDMAC_1_RD_SS3
116,EDOMAIN_DANCING_SURF
117,EDOMAIN_HAIDI_LINE_WR
118,SYNC_irq_intl59v_st1
119,SYNC_irq_vi4_set_2
120,TMU_pulc_ch2
121,TMU_int_occh3SP
122,INTC_XINT *IRQEXT
123,TCU_T4F_INT
124,postman_RCVINT7
125,postman_FIFOINT7
126,Eeko_TIMER_OC7_INT*ASYMMETRIC
127,Eeko_TIMER_IC7_INT*ASYMMETRIC
128,EDOMAIN_SYNGEN_2_A
129,EDOMAIN_EDMAC_1_WR_M0
130,EDOMAIN_EDMAC_7_WR_S0
131,EDOMAIN_EDMAC_2_RD_M0
132,EDOMAIN_DANCING_RACI
133,EDOMAIN_SHREK
134,SYNC_irq_intl50v
135,SYNC_irq_vi4_set_3
136,TMU_pulc_ch3
137,TMU_int_occh3EP
138,INTC_XINT *IRQEXT
139,TCU_IPCOUT5
140,postman_DIRECTINT0
141,postman_Semaphore0
142,Eeko_TIMER_ICOC_OC0INT*ASYMMETRIC
143,Eeko_TIMER_ICOC_IC0INT*ASYMMETRIC
144,EDOMAIN_SYNGEN_3_A
145,EDOMAIN_EDMAC_1_WR_M1
146,EDOMAIN_EDMAC_7_WR_S1
147,EDOMAIN_EDMAC_2_RD_S0
148,EDOMAIN_WOMBAT_INTEG
149,EDOMAIN_SUSAN
150,SYNC_irq_intl50v_st1
151,SYNC_irq_intvi4b
152,Camif
153,TMU_int_occh4SP
154,INTC_XINT *IRQEXT
155,TCU_T5F_INT
156,postman_DIRECTINT1
157,postman_Semaphore1
158,Eeko_TIMER_ICOC_OC1INT*ASYMMETRIC
159,Eeko_TIMER_ICOC_IC1INT*ASYMMETRIC
160,EDOMAIN_SYNGEN_4_A
161,EDOMAIN_EDMAC_1_WR_M2
162,EDOMAIN_EDMAC_7_WR_SS0
163,EDOMAIN_EDMAC_2_RD_SS0
164,EDOMAIN_WOMBAT_BLOCK
165,EDOMAIN_OHYITG
166,SYNC_irq_intlssdv
167,SYNC_irq_vi4b_set_1
168,Camif
169,TMU_int_occh4EP
170,INTC_XINT *IRQEXT
171,Aproc_irq_aproc
172,postman_DIRECTINT2
173,postman_Semaphore2
174,rem_REM_INT
175,zico_timer_irq
176,EDOMAIN_SYNGEN_STP_A
177,EDOMAIN_EDMAC_1_WR_M3
178,EDOMAIN_EDMAC_ATO_WR_SS0
179,EDOMAIN_EDMAC_3_RD_M0
180,EDOMAIN_WOMBAT_AE
181,EDOMAIN_HIP
182,SYNC_irq_intlssdv_st1
183,SYNC_irq_vi4b_set_2
184,Camif
185,TMU_int_occh5SP
186,INTC_XINT *IRQEXT
187,Aproc_irq_aproc
188,postman_DIRECTINT3
189,postman_Semaphore3
190,SDDomain_ADMAC0
191,HDMAC0_IntrReq1
192,EDOMAIN_SYNGEN_FRM_A
193,EDOMAIN_EDMAC_1_WR_M4
194,EDOMAIN_EDMAC_ATO_WR_SS1
195,EDOMAIN_EDMAC_3_RD_OPT_RICH
196,EDOMAIN_COMBAT_INTEG
197,EDOMAIN_RASH
198,SYNC_irq_intp
199,SYNC_irq_vi4b_set_3
200,Camif
201,TMU_int_occh5EP
202,INTC_XINT *IRQEXT
203,Aproc_irq_aproc
204,postman_DIRECTINT4
205,postman_fifi_err0
206,SDDomain_ADMAC1
207,HDMAC0_IntrReq2
208,EDOMAIN_SYNGEN_1_B
209,EDOMAIN_EDMAC_1_WR_S0
210,EDOMAIN_EDMAC_ATO_WR_SS2
211,EDOMAIN_EDMAC_3_RD_OPT_LITE
212,EDOMAIN_COMBAT_BLOCK
213,EDOMAIN_RSHD
214,SYNC_irq_intp_st1
215,SYNC_vi_out12
216,Camif
217,TMU_int_icapch0
218,INTC_XINT *IRQEXT
219,Aproc_irq_aproc
220,postman_DIRECTINT5
221,SATA_irq_sata
222,SDDomain_ADMAC2
223,HDMAC0_IntrReq3
224,EDOMAIN_SYNGEN_2_B
225,EDOMAIN_EDMAC_1_WR_SS0
226,EDOMAIN_ORCA_1
227,EDOMAIN_EDMAC_DAF_RD_M0
228,EDOMAIN_WEABER1
229,(reserved)
230,SYNC_irq_inte
231,Camif
232,Camif
233,TMU_int_icapch1
234,INTC_XINT *IRQEXT
235,Aproc_irq_aproc
236,postman_DIRECTINT6
237,PCIe_irq_pcie
238,SDDomain_SDCON0
239,HDMAC0_IntrReq4
240,EDOMAIN_SYNGEN_3_B
241,EDOMAIN_EDMAC_1_WR_SS1
242,EDOMAIN_ORCA_2
243,EDOMAIN_EDMAC_DAF_RD_S0
244,EDOMAIN_WEABER2
245,(reserved)
246,SYNC_irq_inte_st1
247,Camif
248,Camif
249,TMU_int_icapch2
250,INTC_XINT *IRQEXT
251,Aproc_irq_aproc
252,postman_DIRECTINT7
253,PCIe_irq_pcie
254,SDDomain_SDCON1
255,HDMAC0_IntrReq5
256,EDOMAIN_SYNGEN_4_B
257,EDOMAIN_EDMAC_1_WR_SS2
258,EDOMAIN_ORCA_3
259,EDOMAIN_EDMAC_DAF_RD_S1
260,EDOMAIN_HISTORY
261,(reserved)
262,SYNC_-
263,SSIO_SSIOINT
264,Camif
265,TMU_int_icapch3
266,INTC_XINT *IRQEXT
267,Aproc_irq_aproc
268,cclime_msgcom_int0
269,PCIe_irq_pcie
270,SDDomain_SDCON2
271,HDMAC0_IntrReq6
272,EDOMAIN_SYNGEN_STP_B
273,EDOMAIN_EDMAC_1_WR_SS3
274,EDOMAIN_ORCA_4
275,EDOMAIN_EDMAC_MAP_RD_S0
276,EDOMAIN_HISTORY2_1
277,(reserved)
278,SYNC_-
279,SIO0_SIO0INT
280,Camif
281,TMU_int_icapch4
282,INTC_XINT *IRQEXT
283,Aproc_irq_aproc
284,cclime_msgcom_int1
285,UHS2_irq_uhs2
286,XDMAC_XDMAC_0
287,HDMAC0_IntrReq7
288,EDOMAIN_SYNGEN_FRM_B
289,EDOMAIN_EDMAC_1_WR_SS4
290,EDOMAIN_ORCA_5
291,EDOMAIN_EDMAC_5_RD_M0
292,EDOMAIN_HISTORY2_2
293,(reserved)
294,SYNC_-
295,SIO1_SIO1INT
296,Camif
297,TMU_int_icapch5
298,INTC_XINT *IRQEXT
299,Aproc_irq_aproc
300,cclime_msgcom_int2
301,UHS2_irq_uhs2
302,XDMAC_XDMAC_1
303,irq_mdomain_i2i_0
304,EDOMAIN_HEAD_ERR/ATOMIC_ERR
305,EDOMAIN_EDMAC_1_WR_SS5
306,EDOMAIN_ORCA_6
307,EDOMAIN_EDMAC_5_RD_M1
308,EDOMAIN_HISTORY2_3
309,(reserved)
310,SYNC_-
311,SIO2_SIO2INT
312,Camif
313,TMU_int_icapch6
314,INTC_XINT *IRQEXT
315,Aproc_irq_aproc
316,cclime_msgcom_int3
317,USB_hibiki_h
318,XDMAC_XDMAC_2
319,irq_mdomain_i2i_1
320,EDOMAIN_HEAD_ERR2
321,EDOMAIN_EDMAC_2_WR_M0
322,EDOMAIN_ORCA_7
323,EDOMAIN_EDMAC_5_RD_S0
324,EDOMAIN_HISTORY2_4
325,(reserved)
326,SYNC_irq_lss
327,SIO3_SIO3INT
328,Camif
329,TMU_int_icapch7
330,INTC_XINT *IRQEXT
331,adomain_xmon0
332,cclime_msgcom_int4
333,USB_hibiki_d
334,XDMAC_XDMAC_3
335,irq_mdomain_i2i_2
336,EDOMAIN_HEAD_ERR3
337,EDOMAIN_EDMAC_2_WR_S0
338,EDOMAIN_ORCA_8
339,EDOMAIN_EDMAC_5_RD_SS0
340,EDOMAIN_BIKING
341,TSENS_irq_tsens
342,SYNC_irq_lss_st1
343,SIO4_SIO4INT
344,Camif
345,TMU_int_icapch8
346,INTC_XINT *IRQEXT
347,adomain_xmon1
348,cclime_msgcom_int5
349,UART0 RX_IntReqRx
350,DSI_irq_dsi
351,irq_mdomain_a2i_cclime
352,EDOMAIN_HEAD_ERR4
353,EDOMAIN_EDMAC_2_WR_SS0
354,EDOMAIN_ORCA_9
355,EDOMAIN_EDMAC_5_RD_SS1
356,EDOMAIN_CAPTAIN
357,XDMAC_XDMAC_ABORT
358,SYNC_vi_out0
359,SIO5_SIO5INT
360,Camif
361,TMU_int_icapch9
362,INCT_XINT *IRQEXT
363,adomain_xmon2
364,cclime_msgcom_int6
365,UART0 TX_IntReqTx
366,HDMI_irq_hdmi
367,SROMC0_oIRQ_TX
368,EDOMAIN_HEAD_ERR5
369,EDOMAIN_EDMAC_3_WR_M0
370,EDOMAIN_SWAN_GV_END
371,EDOMAIN_EDMAC_5_RD_SS2
372,EDOMAIN_OPTI0
373,SYNC_vi_out13
374,SYNC_vi_out1
375,SIO6_SIO6INT
376,mario_mario
377,TMU_int_icapch10
378,INTC_XINT *IRQEXT
379,adomain_xmon3
380,cclime_msgcom_int7
381,UART1 RX_IntReqRx
382,HDMI_irq_hdmi
383,SROMC0_oIRQ_RX
384,EDOMAIN_HEAD_ERR6
385,EDOMAIN_EDMAC_3_WR_S0
386,EDOMAIN_PLANET_WR_0
387,EDOMAIN_EDMAC_6_RD_S0
388,EDOMAIN_OPTI1
389,SYNC_vi_out14
390,SYNC_vi_out2
391,SIO7_SIO7INT
392,mario_mario
393,TMU_int_icapch11
394,INTC_XINT *IRQEXT
395,cclime_citron_int
396,cclime_sdcon_int
397,UART1 TX_IntReqTx
398,PMU_irq_pmu
399,SROMC0_oIRQ_FAULT
400,EDOMAIN_SAP1
401,EDOMAIN_EDMAC_3_WR_SS0
402,EDOMAIN_PLANET_WR_1
403,EDOMAIN_EDMAC_6_RD_S1
404,EDOMAIN_DAFIGARO
405,SYNC_vi_out15
406,SYNC_vi_out3
407,swimmy_irq_sitter
408,mario_mario
409,TMU_INT_SWA_ONLY
410,INTC_XINT *IRQEXT
411,cclime_tdmac0_int
412,cclime_others_int
413,UART2 RX_IntReqRx
414,HARB_harbInt
415,SROMC0_oERR_COLLECT
416,EDOMAIN_SAP2
417,EDOMAIN_EDMAC_DAF_WR_S0
418,EDOMAIN_PLANET_RD_0
419,EDOMAIN_EDMAC_6_RD_SS0
420,EDOMAIN_EDMAC_6_RD_SS5
421,SYNC_irq_intvi5
422,SYNC_vi_out4
423,swimmy_irq_endev
424,mario_mario
425,TMU_INT_SWB_ONLY
426,INCT_XINT *IRQEXT
427,cclime_tdmac1_int
428,cclime_slotb_sddat1_int *IRQEXT
429,UART2 TX_IntReqTx
430,RSTGEN_WDTINT
431,SROMC1_oIRQ_TX
432,EDOMAIN_SAP3
433,EDOMAIN_EDMAC_MAP_WR_SS0
434,EDOMAIN_PLANET_RD_1
435,EDOMAIN_EDMAC_6_RD_SS1
436,EDOMAIN_EDMAC_6_RD_SS6
437,dolphin
438,SYNC_vi_out5
439,swimmy_irq_sven
440,mario_mario
441,TMU_INT_SWC_ONLY
442,INTC_XINT *IRQEXT
443,cclime_tdmac2_int
444,cclime_slotd_sddat1_int *IRQEXT
445,I2C0_TIRQ
446,I2C1_TIRQ
447,SROMC1_oIRQ_RX
448,EDOMAIN_ATOMIC_LIP
449,EDOMAIN_EDMAC_MAP_WR_SS1
450,EDOMAIN_JP52
451,EDOMAIN_EDMAC_6_RD_SS2
452,EDOMAIN_EDMAC_6_RD_SS7
453,dolphin
454,SYNC_vi_out6
455,ALGS_irq_algs
456,mario_mario
457,TMU_INT_SWD_ONLY
458,INTC_IRQ_soft_out*ASYMMETRIC
459,cclime_tdmac3_int
460,(reserved)
461,I2C0_RIRQ
462,I2C1_RIRQ
463,SROMC1_oIRQ_FAULT
464,EDOMAIN_PENTA
465,EDOMAIN_EDMAC_5_WR_M0
466,EDOMAIN_EDMAC_OPERA_WR
467,EDOMAIN_EDMAC_6_RD_SS3
468,EDOMAIN_EDMAC_DAN_RD
469,dolphin
470,int_tm_misc_cpu_handshake0*ASYMMETRIC
471,ALGS_irq_algs
472,mario_mario
473,irq_mcpu_SCUEVABORT *IRQEXT
474,irq_mcpu_SLVERRINTR
475,irq_mcpu
476,(reserved)
477,I2C0_SIRQ
478,I2C1_SIRQ
479,SROMC1_oERR_COLLECT
480,EDOMAIN_SANTA
481,EDOMAIN_EDMAC_5_WR_S0
482,EDOMAIN_EDMAC_OPERA_RD
483,EDOMAIN_EDMAC_6_RD_SS4
484,EDOMAIN_EDMAC_7_RD_S0
485,dolphin
486,int_tm_misc_cpu_handshake1*ASYMMETRIC
487,GLDA_irq_glda
488,mario_mario
489,irq_mcpu_DECERRINTR
490,irq_mcpu_L2CCINTR
491,irq_mcpu
492,MONI_moniout(0)*IRQEXT
493,MONI_moniout(1)*IRQEXT
494,MONI_moniout(2)*IRQEXT
495,MONI_moniout(3)*IRQEXT
496,INTC_ANDINT(0)*ASYMMETRIC
497,INTC_ANDINT(1)*ASYMMETRIC
498,INTC_ANDINT(2)*ASYMMETRIC
499,INTC_ANDINT(3)*ASYMMETRIC
500,INTC_ANDINT(4)*ASYMMETRIC
501,INTC_ANDINT(5)*ASYMMETRIC
502,DEBSIO
503,XIMR_irq_ximr
504,mario_mario
505,irq_mcpu_ECNTRINTR
506,INTC_ANDINT(0)*ASYMMETRIC
507,INTC_ANDINT(1)*ASYMMETRIC
508,INTC_ANDINT(2)*ASYMMETRIC
509,INTC_ANDINT(3)*ASYMMETRIC
510,INTC_ANDINT(4)*ASYMMETRIC
511,INTC_ANDINT(5)*ASYMMETRIC
512,GIC_SGI(0)
513,GIC_SGI(1)
514,GIC_SGI(2)
515,GIC_SGI(3)
516,GIC_SGI(4)
517,GIC_SGI(5)
518,GIC_SGI(6)
519,GIC_SGI(7)
520,GIC_SGI(8)
521,GIC_SGI(9)
522,GIC_scheduling
523,GIC_timer
524,GIC_suspend
525,GIC_SGI(13)
526,GIC_SGI(14)
527,GIC_SGI(15)
528,GIC_PPI(16)
529,GIC_PPI(17)
530,GIC_PPI(18)
531,GIC_PPI(19)
532,GIC_PPI(20)
533,GIC_PPI(21)
534,GIC_PPI(22)
535,GIC_PPI(23)
536,GIC_PPI(24)
537,GIC_PPI(25)
538,GIC_PPI(26)
539,GIC_GlobalTimer
540,GIC_LegacyFiq
541,GIC_PrivateTimer
542,GIC_WatchdogTimer
543,GIC_LegacyIrq
544,GIC_MariusIntc
545,GIC_OmarIntc
546,GIC_SPI(34)
547,GIC_SPI(35)
548,GIC_SPI(36)
549,GIC_SPI(37)
550,GIC_SPI(38)
551,GIC_SPI(39)
552,GIC_SPI(40)
553,GIC_SPI(41)
554,GIC_SPI(42)
555,GIC_SPI(43)
556,GIC_SPI(44)
557,GIC_SPI(45)
558,GIC_SPI(46)
559,GIC_SPI(47)
560,GIC_SPI(48)
561,GIC_SPI(49)
562,GIC_SPI(50)
563,GIC_SPI(51)
564,GIC_SPI(52)
565,GIC_SPI(53)
566,GIC_SPI(54)
567,GIC_SPI(55)
568,GIC_SPI(56)
569,GIC_SPI(57)
570,GIC_SPI(58)
571,GIC_SPI(59)
572,GIC_SPI(60)
573,GIC_SPI(61)
574,GIC_SPI(62)
575,GIC_SPI(63)
<=-=-=- Vector End -=-=-=>
We do now know the meaning of all interrupt sources. This should help to improve qemu support. Vector table is the same on R and M50 so I assue that this table is valid for all DIGIC 8 models.
I have created a canon basic script which saves the interrupt names to SD card and can easily be adjusted for other models. Vectors are stored as hex instead of decimal here:
'Get RP Interrupt Vector Table
dim pIvt_table_1 = 0x1ba48
dim vector1_len = 0x200
dim pIvt_table_2 = 0x1c3ec
dim vector2_len = 0x40
private sub write_table(hFile, pVectorTable, startVector, numElements)
isrVector = startVector
do while isrVector < numElements
ppIrqName = pVectorTable + isrVector * 4
WriteFileString(hFile, "0x%03X: %s\n", isrVector, *ppIrqName)
isrVector = isrVector + 1
loop
end sub
private sub save_ivt(fileName)
RemoveFile(fileName)
hFile = OpenFileCREAT(fileName)
CloseFile(hFile)
hFile = OpenFileWR(fileName)
write_table(hFile, pIvt_table_1, 0, vector1_len)
write_table(hFile, pIvt_table_2, vector1_len, vector2_len)
CloseFile(hFile)
end sub
private sub Initialize()
save_ivt("B:/RP_IVT.TXT")
end sub
Output on RP is:
0x000: -noise-
0x001: EDOMAIN_OPERA_OPEKICK0
0x002: EDOMAIN_EDMAC_5_WR_S1
0x003: EDOMAIN_EDMAC_1_RD_L0
0x004: EDOMAIN_VITON
0x005: EDOMAIN_OPERA0
0x006: SYNC_irq_intb60v
0x007: SYNC_vi_out7
0x008: TMU_int_SWA
0x009: TMU_int_pulc
0x00A: INTC_XINT *IRQEXT
0x00B: TCU_T0OUT *IRQEXT
0x00C: postman_RCVINT0
0x00D: postman_FIFOINT0
0x00E: Eeko_TIMER_OC0_INT*ASYMMETRIC
0x00F: Eeko_TIMER_IC0_INT*ASYMMETRIC
0x010: EDOMAIN_SYNGEN_1
0x011: EDOMAIN_OPERA_OPEKICK1
0x012: EDOMAIN_EDMAC_6_WR_S0
0x013: EDOMAIN_EDMAC_1_RD_M0
0x014: EDOMAIN_AFFINE
0x015: EDOMAIN_OPERA_ERR0
0x016: SYNC_irq_intb59v
0x017: SYNC_vi_out8
0x018: TMU_int_SWB
0x019: TMU_int_occh0SP
0x01A: INTC_XINT *IRQEXT
0x01B: TCU_T1OUT *IRQEXT
0x01C: postman_RCVINT1
0x01D: postman_FIFOINT1
0x01E: Eeko_TIMER_OC1_INT*ASYMMETRIC
0x01F: Eeko_TIMER_IC1_INT*ASYMMETRIC
0x020: EDOMAIN_SYNGEN_2
0x021: EDOMAIN_OPERA_OPEKICK2
0x022: EDOMAIN_EDMAC_6_WR_SS0
0x023: EDOMAIN_EDMAC_1_RD_S0
0x024: EDOMAIN_AFFINE_OVR_ERR
0x025: EDOMAIN_OPERA_ABORT0
0x026: SYNC_irq_intb50v
0x027: SYNC_vi_out9
0x028: TMU_int_ocall
0x029: TMU_int_occh0EP
0x02A: INTC_XINT *IRQEXT
0x02B: TCU_T2OUT *IRQEXT
0x02C: postman_RCVINT2
0x02D: postman_FIFOINT2
0x02E: Eeko_TIMER_OC2_INT*ASYMMETRIC
0x02F: Eeko_TIMER_IC2_INT*ASYMMETRIC
0x030: EDOMAIN_SYNGEN_3
0x031: EDOMAIN_OPERA_OPEKICK3
0x032: EDOMAIN_EDMAC_6_WR_SS1
0x033: EDOMAIN_EDMAC_1_RD_S1
0x034: EDOMAIN_SARIDON
0x035: EDOMAIN_OPERA1
0x036: SYNC_irq_intb49v
0x037: SYNC_vi_out10
0x038: TMU_int_pulgenCEI
0x039: TMU_int_occh1SP
0x03A: INTC_XINT *IRQEXT
0x03B: TCU_T3OUT *IRQEXT
0x03C: postman_RCVINT3
0x03D: postman_FIFOINT3
0x03E: Eeko_TIMER_OC3_INT*ASYMMETRIC
0x03F: Eeko_TIMER_IC3_INT*ASYMMETRIC
0x040: EDOMAIN_SYNGEN_4
0x041: EDOMAIN_OPERA_OPEKICK4
0x042: EDOMAIN_EDMAC_6_WR_SS2
0x043: EDOMAIN_EDMAC_1_RD_SS0
0x044: EDOMAIN_KURABO
0x045: EDOMAIN_OPERA_ERR1
0x046: SYNC_irq_intl60v
0x047: SYNC_vi_out11
0x048: TMU_int_icapCE1
0x049: TMU_int_occh1EP
0x04A: INTC_XINT *IRQEXT
0x04B: TCU_T4OUT *IRQEXT
0x04C: postman_RCVINT4
0x04D: postman_FIFOINT4
0x04E: Eeko_TIMER_OC4_INT*ASYMMETRIC
0x04F: Eeko_TIMER_IC4_INT*ASYMMETRIC
0x050: EDOMAIN_SYNGEN_STP
0x051: EDOMAIN_OPERA_OPEKICK5
0x052: EDOMAIN_EDMAC_6_WR_SS3
0x053: EDOMAIN_EDMAC_1_RD_SS1
0x054: EDOMAIN_MESSI
0x055: EDOMAIN_OPERA_ABORT1
0x056: SYNC_irq_intl60v_st1
0x057: SYNC_irq_intvi4
0x058: TMU_pulc_ch0
0x059: TMU_int_occh2SP
0x05A: INTC_XINT *IRQEXT
0x05B: TCU_T5OUT *IRQEXT
0x05C: postman_RCVINT5
0x05D: postman_FIFOINT5
0x05E: Eeko_TIMER_OC5_INT*ASYMMETRIC
0x05F: Eeko_TIMER_IC5_INT*ASYMMETRIC
0x060: EDOMAIN_SYNGEN_FRM
0x061: EDOMAIN_OPERA_OPEKICK6
0x062: EDOMAIN_EDMAC_6_WR_SS4
0x063: EDOMAIN_EDMAC_1_RD_SS2
0x064: EDOMAIN_DANCING_FEN
0x065: EDOMAIN_HAIDI_PNL_WR
0x066: SYNC_irq_intl59v
0x067: SYNC_irq_vi4_set_1
0x068: TMU_pulc_ch1
0x069: TMU_int_occh2EP
0x06A: INTC_XINT *IRQEXT
0x06B: TCU_IPCOUT4
0x06C: postman_RCVINT6
0x06D: postman_FIFOINT6
0x06E: Eeko_TIMER_OC6_INT*ASYMMETRIC
0x06F: Eeko_TIMER_IC6_INT*ASYMMETRIC
0x070: EDOMAIN_SYNGEN_1_A
0x071: EDOMAIN_EDMAC_1_WR_L0
0x072: EDOMAIN_EDMAC_DAN_WR
0x073: EDOMAIN_EDMAC_1_RD_SS3
0x074: EDOMAIN_DANCING_SURF
0x075: EDOMAIN_HAIDI_LINE_WR
0x076: SYNC_irq_intl59v_st1
0x077: SYNC_irq_vi4_set_2
0x078: TMU_pulc_ch2
0x079: TMU_int_occh3SP
0x07A: INTC_XINT *IRQEXT
0x07B: TCU_T4F_INT
0x07C: postman_RCVINT7
0x07D: postman_FIFOINT7
0x07E: Eeko_TIMER_OC7_INT*ASYMMETRIC
0x07F: Eeko_TIMER_IC7_INT*ASYMMETRIC
0x080: EDOMAIN_SYNGEN_2_A
0x081: EDOMAIN_EDMAC_1_WR_M0
0x082: EDOMAIN_EDMAC_7_WR_S0
0x083: EDOMAIN_EDMAC_2_RD_M0
0x084: EDOMAIN_DANCING_RACI
0x085: EDOMAIN_SHREK
0x086: SYNC_irq_intl50v
0x087: SYNC_irq_vi4_set_3
0x088: TMU_pulc_ch3
0x089: TMU_int_occh3EP
0x08A: INTC_XINT *IRQEXT
0x08B: TCU_IPCOUT5
0x08C: postman_DIRECTINT0
0x08D: postman_Semaphore0
0x08E: Eeko_TIMER_ICOC_OC0INT*ASYMMETRIC
0x08F: Eeko_TIMER_ICOC_IC0INT*ASYMMETRIC
0x090: EDOMAIN_SYNGEN_3_A
0x091: EDOMAIN_EDMAC_1_WR_M1
0x092: EDOMAIN_EDMAC_7_WR_S1
0x093: EDOMAIN_EDMAC_2_RD_S0
0x094: EDOMAIN_WOMBAT_INTEG
0x095: EDOMAIN_SUSAN
0x096: SYNC_irq_intl50v_st1
0x097: SYNC_irq_intvi4b
0x098: Camif
0x099: TMU_int_occh4SP
0x09A: INTC_XINT *IRQEXT
0x09B: TCU_T5F_INT
0x09C: postman_DIRECTINT1
0x09D: postman_Semaphore1
0x09E: Eeko_TIMER_ICOC_OC1INT*ASYMMETRIC
0x09F: Eeko_TIMER_ICOC_IC1INT*ASYMMETRIC
0x0A0: EDOMAIN_SYNGEN_4_A
0x0A1: EDOMAIN_EDMAC_1_WR_M2
0x0A2: EDOMAIN_EDMAC_7_WR_SS0
0x0A3: EDOMAIN_EDMAC_2_RD_SS0
0x0A4: EDOMAIN_WOMBAT_BLOCK
0x0A5: EDOMAIN_OHYITG
0x0A6: SYNC_irq_intlssdv
0x0A7: SYNC_irq_vi4b_set_1
0x0A8: Camif
0x0A9: TMU_int_occh4EP
0x0AA: INTC_XINT *IRQEXT
0x0AB: Aproc_irq_aproc
0x0AC: postman_DIRECTINT2
0x0AD: postman_Semaphore2
0x0AE: rem_REM_INT
0x0AF: zico_timer_irq
0x0B0: EDOMAIN_SYNGEN_STP_A
0x0B1: EDOMAIN_EDMAC_1_WR_M3
0x0B2: EDOMAIN_EDMAC_ATO_WR_SS0
0x0B3: EDOMAIN_EDMAC_3_RD_M0
0x0B4: EDOMAIN_WOMBAT_AE
0x0B5: EDOMAIN_HIP
0x0B6: SYNC_irq_intlssdv_st1
0x0B7: SYNC_irq_vi4b_set_2
0x0B8: Camif
0x0B9: TMU_int_occh5SP
0x0BA: INTC_XINT *IRQEXT
0x0BB: Aproc_irq_aproc
0x0BC: postman_DIRECTINT3
0x0BD: postman_Semaphore3
0x0BE: SDDomain_ADMAC0
0x0BF: HDMAC0_IntrReq1
0x0C0: EDOMAIN_SYNGEN_FRM_A
0x0C1: EDOMAIN_EDMAC_1_WR_M4
0x0C2: EDOMAIN_EDMAC_ATO_WR_SS1
0x0C3: EDOMAIN_EDMAC_3_RD_OPT_RICH
0x0C4: EDOMAIN_COMBAT_INTEG
0x0C5: EDOMAIN_RASH
0x0C6: SYNC_irq_intp
0x0C7: SYNC_irq_vi4b_set_3
0x0C8: Camif
0x0C9: TMU_int_occh5EP
0x0CA: INTC_XINT *IRQEXT
0x0CB: Aproc_irq_aproc
0x0CC: postman_DIRECTINT4
0x0CD: postman_fifi_err0
0x0CE: SDDomain_ADMAC1
0x0CF: HDMAC0_IntrReq2
0x0D0: EDOMAIN_SYNGEN_1_B
0x0D1: EDOMAIN_EDMAC_1_WR_S0
0x0D2: EDOMAIN_EDMAC_ATO_WR_SS2
0x0D3: EDOMAIN_EDMAC_3_RD_OPT_LITE
0x0D4: EDOMAIN_COMBAT_BLOCK
0x0D5: EDOMAIN_RSHD
0x0D6: SYNC_irq_intp_st1
0x0D7: SYNC_vi_out12
0x0D8: Camif
0x0D9: TMU_int_icapch0
0x0DA: INTC_XINT *IRQEXT
0x0DB: Aproc_irq_aproc
0x0DC: postman_DIRECTINT5
0x0DD: SATA_irq_sata
0x0DE: SDDomain_ADMAC2
0x0DF: HDMAC0_IntrReq3
0x0E0: EDOMAIN_SYNGEN_2_B
0x0E1: EDOMAIN_EDMAC_1_WR_SS0
0x0E2: EDOMAIN_ORCA_1
0x0E3: EDOMAIN_EDMAC_DAF_RD_M0
0x0E4: EDOMAIN_WEABER1
0x0E5: (reserved)
0x0E6: SYNC_irq_inte
0x0E7: Camif
0x0E8: Camif
0x0E9: TMU_int_icapch1
0x0EA: INTC_XINT *IRQEXT
0x0EB: Aproc_irq_aproc
0x0EC: postman_DIRECTINT6
0x0ED: PCIe_irq_pcie
0x0EE: SDDomain_SDCON0
0x0EF: HDMAC0_IntrReq4
0x0F0: EDOMAIN_SYNGEN_3_B
0x0F1: EDOMAIN_EDMAC_1_WR_SS1
0x0F2: EDOMAIN_ORCA_2
0x0F3: EDOMAIN_EDMAC_DAF_RD_S0
0x0F4: EDOMAIN_WEABER2
0x0F5: (reserved)
0x0F6: SYNC_irq_inte_st1
0x0F7: Camif
0x0F8: Camif
0x0F9: TMU_int_icapch2
0x0FA: INTC_XINT *IRQEXT
0x0FB: Aproc_irq_aproc
0x0FC: postman_DIRECTINT7
0x0FD: PCIe_irq_pcie
0x0FE: SDDomain_SDCON1
0x0FF: HDMAC0_IntrReq5
0x100: EDOMAIN_SYNGEN_4_B
0x101: EDOMAIN_EDMAC_1_WR_SS2
0x102: EDOMAIN_ORCA_3
0x103: EDOMAIN_EDMAC_DAF_RD_S1
0x104: EDOMAIN_HISTORY
0x105: (reserved)
0x106: SYNC_-
0x107: SSIO_SSIOINT
0x108: Camif
0x109: TMU_int_icapch3
0x10A: INTC_XINT *IRQEXT
0x10B: Aproc_irq_aproc
0x10C: cclime_msgcom_int0
0x10D: PCIe_irq_pcie
0x10E: SDDomain_SDCON2
0x10F: HDMAC0_IntrReq6
0x110: EDOMAIN_SYNGEN_STP_B
0x111: EDOMAIN_EDMAC_1_WR_SS3
0x112: EDOMAIN_ORCA_4
0x113: EDOMAIN_EDMAC_MAP_RD_S0
0x114: EDOMAIN_HISTORY2_1
0x115: (reserved)
0x116: SYNC_-
0x117: SIO0_SIO0INT
0x118: Camif
0x119: TMU_int_icapch4
0x11A: INTC_XINT *IRQEXT
0x11B: Aproc_irq_aproc
0x11C: cclime_msgcom_int1
0x11D: UHS2_irq_uhs2
0x11E: XDMAC_XDMAC_0
0x11F: HDMAC0_IntrReq7
0x120: EDOMAIN_SYNGEN_FRM_B
0x121: EDOMAIN_EDMAC_1_WR_SS4
0x122: EDOMAIN_ORCA_5
0x123: EDOMAIN_EDMAC_5_RD_M0
0x124: EDOMAIN_HISTORY2_2
0x125: (reserved)
0x126: SYNC_-
0x127: SIO1_SIO1INT
0x128: Camif
0x129: TMU_int_icapch5
0x12A: INTC_XINT *IRQEXT
0x12B: Aproc_irq_aproc
0x12C: cclime_msgcom_int2
0x12D: UHS2_irq_uhs2
0x12E: XDMAC_XDMAC_1
0x12F: irq_mdomain_i2i_0
0x130: EDOMAIN_HEAD_ERR/ATOMIC_ERR
0x131: EDOMAIN_EDMAC_1_WR_SS5
0x132: EDOMAIN_ORCA_6
0x133: EDOMAIN_EDMAC_5_RD_M1
0x134: EDOMAIN_HISTORY2_3
0x135: (reserved)
0x136: SYNC_-
0x137: SIO2_SIO2INT
0x138: Camif
0x139: TMU_int_icapch6
0x13A: INTC_XINT *IRQEXT
0x13B: Aproc_irq_aproc
0x13C: cclime_msgcom_int3
0x13D: USB_hibiki_h
0x13E: XDMAC_XDMAC_2
0x13F: irq_mdomain_i2i_1
0x140: EDOMAIN_HEAD_ERR2
0x141: EDOMAIN_EDMAC_2_WR_M0
0x142: EDOMAIN_ORCA_7
0x143: EDOMAIN_EDMAC_5_RD_S0
0x144: EDOMAIN_HISTORY2_4
0x145: (reserved)
0x146: SYNC_irq_lss
0x147: SIO3_SIO3INT
0x148: Camif
0x149: TMU_int_icapch7
0x14A: INTC_XINT *IRQEXT
0x14B: adomain_xmon0
0x14C: cclime_msgcom_int4
0x14D: USB_hibiki_d
0x14E: XDMAC_XDMAC_3
0x14F: irq_mdomain_i2i_2
0x150: EDOMAIN_HEAD_ERR3
0x151: EDOMAIN_EDMAC_2_WR_S0
0x152: EDOMAIN_ORCA_8
0x153: EDOMAIN_EDMAC_5_RD_SS0
0x154: EDOMAIN_BIKING
0x155: TSENS_irq_tsens
0x156: SYNC_irq_lss_st1
0x157: SIO4_SIO4INT
0x158: Camif
0x159: TMU_int_icapch8
0x15A: INTC_XINT *IRQEXT
0x15B: adomain_xmon1
0x15C: cclime_msgcom_int5
0x15D: UART0 RX_IntReqRx
0x15E: DSI_irq_dsi
0x15F: irq_mdomain_a2i_cclime
0x160: EDOMAIN_HEAD_ERR4
0x161: EDOMAIN_EDMAC_2_WR_SS0
0x162: EDOMAIN_ORCA_9
0x163: EDOMAIN_EDMAC_5_RD_SS1
0x164: EDOMAIN_CAPTAIN
0x165: XDMAC_XDMAC_ABORT
0x166: SYNC_vi_out0
0x167: SIO5_SIO5INT
0x168: Camif
0x169: TMU_int_icapch9
0x16A: INCT_XINT *IRQEXT
0x16B: adomain_xmon2
0x16C: cclime_msgcom_int6
0x16D: UART0 TX_IntReqTx
0x16E: HDMI_irq_hdmi
0x16F: SROMC0_oIRQ_TX
0x170: EDOMAIN_HEAD_ERR5
0x171: EDOMAIN_EDMAC_3_WR_M0
0x172: EDOMAIN_SWAN_GV_END
0x173: EDOMAIN_EDMAC_5_RD_SS2
0x174: EDOMAIN_OPTI0
0x175: SYNC_vi_out13
0x176: SYNC_vi_out1
0x177: SIO6_SIO6INT
0x178: mario_mario
0x179: TMU_int_icapch10
0x17A: INTC_XINT *IRQEXT
0x17B: adomain_xmon3
0x17C: cclime_msgcom_int7
0x17D: UART1 RX_IntReqRx
0x17E: HDMI_irq_hdmi
0x17F: SROMC0_oIRQ_RX
0x180: EDOMAIN_HEAD_ERR6
0x181: EDOMAIN_EDMAC_3_WR_S0
0x182: EDOMAIN_PLANET_WR_0
0x183: EDOMAIN_EDMAC_6_RD_S0
0x184: EDOMAIN_OPTI1
0x185: SYNC_vi_out14
0x186: SYNC_vi_out2
0x187: SIO7_SIO7INT
0x188: mario_mario
0x189: TMU_int_icapch11
0x18A: INTC_XINT *IRQEXT
0x18B: cclime_citron_int
0x18C: cclime_sdcon_int
0x18D: UART1 TX_IntReqTx
0x18E: PMU_irq_pmu
0x18F: SROMC0_oIRQ_FAULT
0x190: EDOMAIN_SAP1
0x191: EDOMAIN_EDMAC_3_WR_SS0
0x192: EDOMAIN_PLANET_WR_1
0x193: EDOMAIN_EDMAC_6_RD_S1
0x194: EDOMAIN_DAFIGARO
0x195: SYNC_vi_out15
0x196: SYNC_vi_out3
0x197: swimmy_irq_sitter
0x198: mario_mario
0x199: TMU_INT_SWA_ONLY
0x19A: INTC_XINT *IRQEXT
0x19B: cclime_tdmac0_int
0x19C: cclime_others_int
0x19D: UART2 RX_IntReqRx
0x19E: HARB_harbInt
0x19F: SROMC0_oERR_COLLECT
0x1A0: EDOMAIN_SAP2
0x1A1: EDOMAIN_EDMAC_DAF_WR_S0
0x1A2: EDOMAIN_PLANET_RD_0
0x1A3: EDOMAIN_EDMAC_6_RD_SS0
0x1A4: EDOMAIN_EDMAC_6_RD_SS5
0x1A5: SYNC_irq_intvi5
0x1A6: SYNC_vi_out4
0x1A7: swimmy_irq_endev
0x1A8: mario_mario
0x1A9: TMU_INT_SWB_ONLY
0x1AA: INCT_XINT *IRQEXT
0x1AB: cclime_tdmac1_int
0x1AC: cclime_slotb_sddat1_int *IRQEXT
0x1AD: UART2 TX_IntReqTx
0x1AE: RSTGEN_WDTINT
0x1AF: SROMC1_oIRQ_TX
0x1B0: EDOMAIN_SAP3
0x1B1: EDOMAIN_EDMAC_MAP_WR_SS0
0x1B2: EDOMAIN_PLANET_RD_1
0x1B3: EDOMAIN_EDMAC_6_RD_SS1
0x1B4: EDOMAIN_EDMAC_6_RD_SS6
0x1B5: dolphin
0x1B6: SYNC_vi_out5
0x1B7: swimmy_irq_sven
0x1B8: mario_mario
0x1B9: TMU_INT_SWC_ONLY
0x1BA: INTC_XINT *IRQEXT
0x1BB: cclime_tdmac2_int
0x1BC: cclime_slotd_sddat1_int *IRQEXT
0x1BD: I2C0_TIRQ
0x1BE: I2C1_TIRQ
0x1BF: SROMC1_oIRQ_RX
0x1C0: EDOMAIN_ATOMIC_LIP
0x1C1: EDOMAIN_EDMAC_MAP_WR_SS1
0x1C2: EDOMAIN_JP52
0x1C3: EDOMAIN_EDMAC_6_RD_SS2
0x1C4: EDOMAIN_EDMAC_6_RD_SS7
0x1C5: dolphin
0x1C6: SYNC_vi_out6
0x1C7: ALGS_irq_algs
0x1C8: mario_mario
0x1C9: TMU_INT_SWD_ONLY
0x1CA: INTC_IRQ_soft_out*ASYMMETRIC
0x1CB: cclime_tdmac3_int
0x1CC: (reserved)
0x1CD: I2C0_RIRQ
0x1CE: I2C1_RIRQ
0x1CF: SROMC1_oIRQ_FAULT
0x1D0: EDOMAIN_PENTA
0x1D1: EDOMAIN_EDMAC_5_WR_M0
0x1D2: EDOMAIN_EDMAC_OPERA_WR
0x1D3: EDOMAIN_EDMAC_6_RD_SS3
0x1D4: EDOMAIN_EDMAC_DAN_RD
0x1D5: dolphin
0x1D6: int_tm_misc_cpu_handshake0*ASYMMETRIC
0x1D7: ALGS_irq_algs
0x1D8: mario_mario
0x1D9: irq_mcpu_SCUEVABORT *IRQEXT
0x1DA: irq_mcpu_SLVERRINTR
0x1DB: irq_mcpu
0x1DC: (reserved)
0x1DD: I2C0_SIRQ
0x1DE: I2C1_SIRQ
0x1DF: SROMC1_oERR_COLLECT
0x1E0: EDOMAIN_SANTA
0x1E1: EDOMAIN_EDMAC_5_WR_S0
0x1E2: EDOMAIN_EDMAC_OPERA_RD
0x1E3: EDOMAIN_EDMAC_6_RD_SS4
0x1E4: EDOMAIN_EDMAC_7_RD_S0
0x1E5: dolphin
0x1E6: int_tm_misc_cpu_handshake1*ASYMMETRIC
0x1E7: GLDA_irq_glda
0x1E8: mario_mario
0x1E9: irq_mcpu_DECERRINTR
0x1EA: irq_mcpu_L2CCINTR
0x1EB: irq_mcpu
0x1EC: MONI_moniout(0)*IRQEXT
0x1ED: MONI_moniout(1)*IRQEXT
0x1EE: MONI_moniout(2)*IRQEXT
0x1EF: MONI_moniout(3)*IRQEXT
0x1F0: INTC_ANDINT(0)*ASYMMETRIC
0x1F1: INTC_ANDINT(1)*ASYMMETRIC
0x1F2: INTC_ANDINT(2)*ASYMMETRIC
0x1F3: INTC_ANDINT(3)*ASYMMETRIC
0x1F4: INTC_ANDINT(4)*ASYMMETRIC
0x1F5: INTC_ANDINT(5)*ASYMMETRIC
0x1F6: DEBSIO
0x1F7: XIMR_irq_ximr
0x1F8: mario_mario
0x1F9: irq_mcpu_ECNTRINTR
0x1FA: INTC_ANDINT(0)*ASYMMETRIC
0x1FB: INTC_ANDINT(1)*ASYMMETRIC
0x1FC: INTC_ANDINT(2)*ASYMMETRIC
0x1FD: INTC_ANDINT(3)*ASYMMETRIC
0x1FE: INTC_ANDINT(4)*ASYMMETRIC
0x1FF: INTC_ANDINT(5)*ASYMMETRIC