Updated autoexec.bin from the first post with the
latest codebase; it now saves all this info to a file.
Results from 5D3 (same as all other DIGIC 5 models):
CHDK CPU info for 0x285 5D3
------------------------------
ID 0x41059461
Revision 0x1 1
Part 0x946 2374
ARM Arch 0x5 5
Variant 0x0 0
Implementor 0x41 65
Cache type 0x0F192192
Icache words/line 0x2 2 [8]
Icache absent 0x0 0
Icache assoc 0x2 2
Icache size 0x6 6 [32K]
Reserved0_2 0x0 0
Dcache words/line 0x2 2 [8]
Dcache absent 0x0 0
Dcache assoc 0x2 2
Dcache size 0x6 6 [32K]
Reserved1_2 0x0 0
Harvard/unified 0x1 1
Cache type 0x7 7
Reserved2_3 0x0 0
TCM type 0x000C00C0
Reserved0_2 0x0 0
ITCM absent 0x0 0
Reserved1_3 0x0 0
ITCM size 0x3 3 [4K]
Reserved2_4 0x0 0
DTCM absent 0x0 0
Reserved3_2 0x0 0
DTCM size 0x3 3 [4K]
Reserved4_10 0x0 0
Control 0x0005107D
Protect enable 0x1 1
Reserved0_1 0x0 0
Dcache enable 0x1 1
Reserved1_4 0xF 15
Big endian 0x0 0
Reserved2_4 0x0 0
Icache enable 0x1 1
Alt vector 0x0 0
Cache RRR 0x0 0
Disble load TBIT 0x0 0
DTCM enable 0x1 1
DTCM mode 0x0 0
ITCM enable 0x1 1
ITCM mode 0x0 0
Reserved3_12 0x0 0
Protection Region 0 0x0000003F
Enable 0x1 1
Size 0x1F 31 [4G]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 1 0x0000003D
Enable 0x1 1
Size 0x1E 30 [2G]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 2 0xE0000039
Enable 0x1 1
Size 0x1C 28 [512M]
Undef0_7 0x0 0
Base 0x70000 458752 [0xE0000000]
Protection Region 3 0xC0000039
Enable 0x1 1
Size 0x1C 28 [512M]
Undef0_7 0x0 0
Base 0x60000 393216 [0xC0000000]
Protection Region 4 0xFF00002F
Enable 0x1 1
Size 0x17 23 [16M]
Undef0_7 0x0 0
Base 0x7F800 522240 [0xFF000000]
Protection Region 5 0x00000039
Enable 0x1 1
Size 0x1C 28 [512M]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 6 0xF700002F
Enable 0x1 1
Size 0x17 23 [16M]
Undef0_7 0x0 0
Base 0x7B800 505856 [0xF7000000]
Protection Region 7 0x00000000
Enable 0x0 0
Size 0x0 0 [invalid]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Region data perms 0x03333333
Region 0 0x3 3 [P:RW U:RW]
Region 1 0x3 3 [P:RW U:RW]
Region 2 0x3 3 [P:RW U:RW]
Region 3 0x3 3 [P:RW U:RW]
Region 4 0x3 3 [P:RW U:RW]
Region 5 0x3 3 [P:RW U:RW]
Region 6 0x3 3 [P:RW U:RW]
Region 7 0x0 0 [P:-- U:--]
Region inst perms 0x03333333
Region 0 0x3 3 [P:RW U:RW]
Region 1 0x3 3 [P:RW U:RW]
Region 2 0x3 3 [P:RW U:RW]
Region 3 0x3 3 [P:RW U:RW]
Region 4 0x3 3 [P:RW U:RW]
Region 5 0x3 3 [P:RW U:RW]
Region 6 0x3 3 [P:RW U:RW]
Region 7 0x0 0 [P:-- U:--]
DCache cfg 0x00000070
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x0 0
Region 3 0x0 0
Region 4 0x1 1
Region 5 0x1 1
Region 6 0x1 1
Region 7 0x0 0
ICache cfg 0x00000070
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x0 0
Region 3 0x0 0
Region 4 0x1 1
Region 5 0x1 1
Region 6 0x1 1
Region 7 0x0 0
Write buffer 0x00000070
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x0 0
Region 3 0x0 0
Region 4 0x1 1
Region 5 0x1 1
Region 6 0x1 1
Region 7 0x0 0
DTCM cfg 0x40000006
Reserved0_1 0x0 0
Size 0x3 3 [4K]
Undef0_7 0x0 0
Base 0x20000 131072 [0x40000000]
ITCM cfg 0x00000006
Reserved0_1 0x0 0
Size 0x3 3 [4K]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
From 500D (similar to other DIGIC 4, minor differences):
CHDK CPU info for 0x252 500D
------------------------------
ID 0x41059461
Revision 0x1 1
Part 0x946 2374
ARM Arch 0x5 5
Variant 0x0 0
Implementor 0x41 65
Cache type 0x0F112112
Icache words/line 0x2 2 [8]
Icache absent 0x0 0
Icache assoc 0x2 2
Icache size 0x4 4 [8K]
Reserved0_2 0x0 0
Dcache words/line 0x2 2 [8]
Dcache absent 0x0 0
Dcache assoc 0x2 2
Dcache size 0x4 4 [8K]
Reserved1_2 0x0 0
Harvard/unified 0x1 1
Cache type 0x7 7
Reserved2_3 0x0 0
TCM type 0x000C00C0
Reserved0_2 0x0 0
ITCM absent 0x0 0
Reserved1_3 0x0 0
ITCM size 0x3 3 [4K]
Reserved2_4 0x0 0
DTCM absent 0x0 0
Reserved3_2 0x0 0
DTCM size 0x3 3 [4K]
Reserved4_10 0x0 0
Control 0x0005107D
Protect enable 0x1 1
Reserved0_1 0x0 0
Dcache enable 0x1 1
Reserved1_4 0xF 15
Big endian 0x0 0
Reserved2_4 0x0 0
Icache enable 0x1 1
Alt vector 0x0 0
Cache RRR 0x0 0
Disble load TBIT 0x0 0
DTCM enable 0x1 1
DTCM mode 0x0 0
ITCM enable 0x1 1
ITCM mode 0x0 0
Reserved3_12 0x0 0
Protection Region 0 0x0000003F
Enable 0x1 1
Size 0x1F 31 [4G]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 1 0x0000003D
Enable 0x1 1
Size 0x1E 30 [2G]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 2 0xE0000039
Enable 0x1 1
Size 0x1C 28 [512M]
Undef0_7 0x0 0
Base 0x70000 458752 [0xE0000000]
Protection Region 3 0xC0000039
Enable 0x1 1
Size 0x1C 28 [512M]
Undef0_7 0x0 0
Base 0x60000 393216 [0xC0000000]
Protection Region 4 0xFF00002F
Enable 0x1 1
Size 0x17 23 [16M]
Undef0_7 0x0 0
Base 0x7F800 522240 [0xFF000000]
Protection Region 5 0x00000039
Enable 0x1 1
Size 0x1C 28 [512M]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 6 0xF780002D
Enable 0x1 1
Size 0x16 22 [8M]
Undef0_7 0x0 0
Base 0x7BC00 506880 [0xF7800000]
Protection Region 7 0x00000000
Enable 0x0 0
Size 0x0 0 [invalid]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Region data perms 0x03333333
Region 0 0x3 3 [P:RW U:RW]
Region 1 0x3 3 [P:RW U:RW]
Region 2 0x3 3 [P:RW U:RW]
Region 3 0x3 3 [P:RW U:RW]
Region 4 0x3 3 [P:RW U:RW]
Region 5 0x3 3 [P:RW U:RW]
Region 6 0x3 3 [P:RW U:RW]
Region 7 0x0 0 [P:-- U:--]
Region inst perms 0x03333333
Region 0 0x3 3 [P:RW U:RW]
Region 1 0x3 3 [P:RW U:RW]
Region 2 0x3 3 [P:RW U:RW]
Region 3 0x3 3 [P:RW U:RW]
Region 4 0x3 3 [P:RW U:RW]
Region 5 0x3 3 [P:RW U:RW]
Region 6 0x3 3 [P:RW U:RW]
Region 7 0x0 0 [P:-- U:--]
DCache cfg 0x00000070
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x0 0
Region 3 0x0 0
Region 4 0x1 1
Region 5 0x1 1
Region 6 0x1 1
Region 7 0x0 0
ICache cfg 0x00000070
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x0 0
Region 3 0x0 0
Region 4 0x1 1
Region 5 0x1 1
Region 6 0x1 1
Region 7 0x0 0
Write buffer 0x00000070
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x0 0
Region 3 0x0 0
Region 4 0x1 1
Region 5 0x1 1
Region 6 0x1 1
Region 7 0x0 0
DTCM cfg 0x40000006
Reserved0_1 0x0 0
Size 0x3 3 [4K]
Undef0_7 0x0 0
Base 0x20000 131072 [0x40000000]
ITCM cfg 0x00000006
Reserved0_1 0x0 0
Size 0x3 3 [4K]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
From 5D2:
CHDK CPU info for 0x218 5D2
------------------------------
ID 0x41059461
Revision 0x1 1
Part 0x946 2374
ARM Arch 0x5 5
Variant 0x0 0
Implementor 0x41 65
Cache type 0x0F112112
Icache words/line 0x2 2 [8]
Icache absent 0x0 0
Icache assoc 0x2 2
Icache size 0x4 4 [8K]
Reserved0_2 0x0 0
Dcache words/line 0x2 2 [8]
Dcache absent 0x0 0
Dcache assoc 0x2 2
Dcache size 0x4 4 [8K]
Reserved1_2 0x0 0
Harvard/unified 0x1 1
Cache type 0x7 7
Reserved2_3 0x0 0
TCM type 0x000C00C0
Reserved0_2 0x0 0
ITCM absent 0x0 0
Reserved1_3 0x0 0
ITCM size 0x3 3 [4K]
Reserved2_4 0x0 0
DTCM absent 0x0 0
Reserved3_2 0x0 0
DTCM size 0x3 3 [4K]
Reserved4_10 0x0 0
Control 0x0005107D
Protect enable 0x1 1
Reserved0_1 0x0 0
Dcache enable 0x1 1
Reserved1_4 0xF 15
Big endian 0x0 0
Reserved2_4 0x0 0
Icache enable 0x1 1
Alt vector 0x0 0
Cache RRR 0x0 0
Disble load TBIT 0x0 0
DTCM enable 0x1 1
DTCM mode 0x0 0
ITCM enable 0x1 1
ITCM mode 0x0 0
Reserved3_12 0x0 0
Protection Region 0 0x0000003F
Enable 0x1 1
Size 0x1F 31 [4G]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 1 0x0000003D
Enable 0x1 1
Size 0x1E 30 [2G]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 2 0xE0000039
Enable 0x1 1
Size 0x1C 28 [512M]
Undef0_7 0x0 0
Base 0x70000 458752 [0xE0000000]
Protection Region 3 0xC0000039
Enable 0x1 1
Size 0x1C 28 [512M]
Undef0_7 0x0 0
Base 0x60000 393216 [0xC0000000]
Protection Region 4 0xFF80002D
Enable 0x1 1
Size 0x16 22 [8M]
Undef0_7 0x0 0
Base 0x7FC00 523264 [0xFF800000]
Protection Region 5 0x00000039
Enable 0x1 1
Size 0x1C 28 [512M]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 6 0xF780002D
Enable 0x1 1
Size 0x16 22 [8M]
Undef0_7 0x0 0
Base 0x7BC00 506880 [0xF7800000]
Protection Region 7 0x00000000
Enable 0x0 0
Size 0x0 0 [invalid]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Region data perms 0x03333333
Region 0 0x3 3 [P:RW U:RW]
Region 1 0x3 3 [P:RW U:RW]
Region 2 0x3 3 [P:RW U:RW]
Region 3 0x3 3 [P:RW U:RW]
Region 4 0x3 3 [P:RW U:RW]
Region 5 0x3 3 [P:RW U:RW]
Region 6 0x3 3 [P:RW U:RW]
Region 7 0x0 0 [P:-- U:--]
Region inst perms 0x03333333
Region 0 0x3 3 [P:RW U:RW]
Region 1 0x3 3 [P:RW U:RW]
Region 2 0x3 3 [P:RW U:RW]
Region 3 0x3 3 [P:RW U:RW]
Region 4 0x3 3 [P:RW U:RW]
Region 5 0x3 3 [P:RW U:RW]
Region 6 0x3 3 [P:RW U:RW]
Region 7 0x0 0 [P:-- U:--]
DCache cfg 0x00000070
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x0 0
Region 3 0x0 0
Region 4 0x1 1
Region 5 0x1 1
Region 6 0x1 1
Region 7 0x0 0
ICache cfg 0x00000070
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x0 0
Region 3 0x0 0
Region 4 0x1 1
Region 5 0x1 1
Region 6 0x1 1
Region 7 0x0 0
Write buffer 0x00000070
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x0 0
Region 3 0x0 0
Region 4 0x1 1
Region 5 0x1 1
Region 6 0x1 1
Region 7 0x0 0
DTCM cfg 0x40000006
Reserved0_1 0x0 0
Size 0x3 3 [4K]
Undef0_7 0x0 0
Base 0x20000 131072 [0x40000000]
ITCM cfg 0x00000006
Reserved0_1 0x0 0
Size 0x3 3 [4K]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
From 7D:
CHDK CPU info for 0x250 7D
------------------------------
ID 0x41059461
Revision 0x1 1
Part 0x946 2374
ARM Arch 0x5 5
Variant 0x0 0
Implementor 0x41 65
Cache type 0x0F112112
Icache words/line 0x2 2 [8]
Icache absent 0x0 0
Icache assoc 0x2 2
Icache size 0x4 4 [8K]
Reserved0_2 0x0 0
Dcache words/line 0x2 2 [8]
Dcache absent 0x0 0
Dcache assoc 0x2 2
Dcache size 0x4 4 [8K]
Reserved1_2 0x0 0
Harvard/unified 0x1 1
Cache type 0x7 7
Reserved2_3 0x0 0
TCM type 0x000C00C0
Reserved0_2 0x0 0
ITCM absent 0x0 0
Reserved1_3 0x0 0
ITCM size 0x3 3 [4K]
Reserved2_4 0x0 0
DTCM absent 0x0 0
Reserved3_2 0x0 0
DTCM size 0x3 3 [4K]
Reserved4_10 0x0 0
Control 0x0005107D
Protect enable 0x1 1
Reserved0_1 0x0 0
Dcache enable 0x1 1
Reserved1_4 0xF 15
Big endian 0x0 0
Reserved2_4 0x0 0
Icache enable 0x1 1
Alt vector 0x0 0
Cache RRR 0x0 0
Disble load TBIT 0x0 0
DTCM enable 0x1 1
DTCM mode 0x0 0
ITCM enable 0x1 1
ITCM mode 0x0 0
Reserved3_12 0x0 0
Protection Region 0 0x0000003F
Enable 0x1 1
Size 0x1F 31 [4G]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 1 0x0000003D
Enable 0x1 1
Size 0x1E 30 [2G]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 2 0xE0000039
Enable 0x1 1
Size 0x1C 28 [512M]
Undef0_7 0x0 0
Base 0x70000 458752 [0xE0000000]
Protection Region 3 0xC0000039
Enable 0x1 1
Size 0x1C 28 [512M]
Undef0_7 0x0 0
Base 0x60000 393216 [0xC0000000]
Protection Region 4 0xFF80002F
Enable 0x1 1
Size 0x17 23 [16M]
Undef0_7 0x0 0
Base 0x7FC00 523264 [0xFF800000]
Protection Region 5 0x00000039
Enable 0x1 1
Size 0x1C 28 [512M]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 6 0x8000002F
Enable 0x1 1
Size 0x17 23 [16M]
Undef0_7 0x0 0
Base 0x40000 262144 [0x80000000]
Protection Region 7 0x00000000
Enable 0x0 0
Size 0x0 0 [invalid]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Region data perms 0x03333333
Region 0 0x3 3 [P:RW U:RW]
Region 1 0x3 3 [P:RW U:RW]
Region 2 0x3 3 [P:RW U:RW]
Region 3 0x3 3 [P:RW U:RW]
Region 4 0x3 3 [P:RW U:RW]
Region 5 0x3 3 [P:RW U:RW]
Region 6 0x3 3 [P:RW U:RW]
Region 7 0x0 0 [P:-- U:--]
Region inst perms 0x03333333
Region 0 0x3 3 [P:RW U:RW]
Region 1 0x3 3 [P:RW U:RW]
Region 2 0x3 3 [P:RW U:RW]
Region 3 0x3 3 [P:RW U:RW]
Region 4 0x3 3 [P:RW U:RW]
Region 5 0x3 3 [P:RW U:RW]
Region 6 0x3 3 [P:RW U:RW]
Region 7 0x0 0 [P:-- U:--]
DCache cfg 0x00000030
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x0 0
Region 3 0x0 0
Region 4 0x1 1
Region 5 0x1 1
Region 6 0x0 0
Region 7 0x0 0
ICache cfg 0x00000030
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x0 0
Region 3 0x0 0
Region 4 0x1 1
Region 5 0x1 1
Region 6 0x0 0
Region 7 0x0 0
Write buffer 0x00000030
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x0 0
Region 3 0x0 0
Region 4 0x1 1
Region 5 0x1 1
Region 6 0x0 0
Region 7 0x0 0
DTCM cfg 0x40000006
Reserved0_1 0x0 0
Size 0x3 3 [4K]
Undef0_7 0x0 0
Base 0x20000 131072 [0x40000000]
ITCM cfg 0x00000006
Reserved0_1 0x0 0
Size 0x3 3 [4K]
Undef0_7 0x0 0
Base 0
From 200D:
CHDK CPU info for 0x417 200D
------------------------------
ID 0x414FC091
Revision 0x1 1
Part 0xC09 3081
ARM Arch 0xF 15
Variant 0x4 4
Implementor 0x41 65
Cache type 0x83338003
Icache min words/line 0x3 3 [8]
(zero) 0x0 0
L1 Icache policy 0x2 2
Dcache min words/line 0x3 3 [8]
Exclusives Reservation Granule 0x3 3 [8]
Cache Writeback Granule 0x3 3 [8]
(zero) 0x0 0
(register format) 0x4 4
TCM type 0x00000000
(raw value) 0x0 0
MPU type 0x414FC091
S 0x1 1
- 0x48 72
Num of MPU regions 0xC0 192
Multiprocessor ID 0x80000000
(raw value) 0x80000000 -2147483648
Processor feature 0 0x00001231
ARM inst set 0x1 1
Thumb inst set 0x3 3
Jazelle inst set 0x2 2
ThumbEE inst set 0x1 1
- 0x0 0
Processor feature 1 0x00000011
Programmers' model 0x1 1
Security extensions 0x1 1
Microcontr. prog model 0x0 0
- 0x0 0
Debug feature 0x00010444
(raw value) 0x10444 66628
Aux feature 0x00000000
(raw value) 0x0 0
Mem model feature 0 0x00100103
VMSA support 0x3 3
PMSA support 0x0 0
Cache coherence 0x1 1
Outer shareable 0x0 0
TCM support 0x0 0
Auxiliary registers 0x1 1
FCSE support 0x0 0
- 0x0 0
Mem model feature 1 0x20000000
L1 Harvard cache VA 0x0 0
L1 unified cache VA 0x0 0
L1 Harvard cache s/w 0x0 0
L1 unified cache s/w 0x0 0
L1 Harvard cache 0x0 0
L1 unified cache 0x0 0
L1 cache test & clean 0x0 0
Branch predictor 0x2 2
Mem model feature 2 0x01230000
L1 Harvard fg prefetch 0x0 0
L1 Harvard bg prefetch 0x0 0
L1 Harvard range 0x0 0
Harvard TLB 0x0 0
Unified TLB 0x3 3
Mem barrier 0x2 2
WFI stall 0x1 1
HW access flag 0x0 0
Mem model feature 3 0x00102111
Cache maintain MVA 0x1 1
Cache maintain s/w 0x1 1
BP maintain 0x1 1
- 0x102 258
Supersection support 0x0 0
ISA feature 0 0x00101111
Swap instrs 0x1 1
Bitcount instrs 0x1 1
Bitfield instrs 0x1 1
CmpBranch instrs 0x1 1
Coproc instrs 0x0 0
Debug instrs 0x1 1
Divide instrs 0x0 0
- 0x0 0
ISA feature 1 0x13112111
Endian instrs 0x1 1
Exception instrs 0x1 1
Exception AR instrs 0x1 1
Extend instrs 0x2 2
IfThen instrs 0x1 1
Immediate instrs 0x1 1
Interwork instrs 0x3 3
Jazelle instrs 0x1 1
ISA feature 2 0x21232041
LoadStore instrs 0x1 1
Memhint instrs 0x4 4
MultiAccess Interruptible instructions 0x0 0
Mult instrs 0x2 2
MultS instrs 0x3 3
MultU instrs 0x2 2
PSR AR instrs 0x1 1
Reversal instrs 0x2 2
ISA feature 3 0x11112131
Saturate instrs 0x1 1
SIMD instrs 0x3 3
SVC instrs 0x1 1
SynchPrim instrs 0x2 2
TabBranch instrs 0x1 1
ThumbCopy instrs 0x1 1
TrueNOP instrs 0x1 1
T2 Exec Env instrs 0x1 1
ISA feature 4 0x00011142
Unprivileged instrs 0x2 2
WithShifts instrs 0x4 4
Writeback instrs 0x1 1
SMC instrs 0x1 1
Barrier instrs 0x1 1
SynchPrim_instrs_frac 0x0 0
PSR_M instrs 0x0 0
- 0x0 0
ISA feature 5 0x00000000
- 0x0 0
Cache level ID 0x09200003
Cache type, level1 0x3 3 [Separate Icache, Dcache]
Cache type, level2 0x0 0 [no cache]
Cache type, level3 0x0 0 [no cache]
Cache type, level4 0x0 0 [no cache]
Cache type, level5 0x0 0 [no cache]
Cache type, level6 0x0 0 [no cache]
Cache type, level7 0x0 0 [no cache]
Cache type, level8 0x1 1 [Icache only]
Level of coherency 0x1 1
Level of unification 0x1 1
(zero) 0x0 0
Cache size ID reg (data, level0) 0x700FE019
Line size in words 0x1 1 [8]
Associativity 0x3 3 [4]
Number of sets 0x7F 127 [128]
Write allocation 0x1 1
Read allocation 0x1 1
Write back 0x1 1
Write through 0x0 0
Cache size ID reg (inst, level0) 0x200FE019
Line size in words 0x1 1 [8]
Associativity 0x3 3 [4]
Number of sets 0x7F 127 [128]
Write allocation 0x0 0
Read allocation 0x1 1
Write back 0x0 0
Write through 0x0 0
SCTLR 0x48C5187D
MPU Enable 0x1 1
Strict Align 0x0 0
L1 DCache Enable 0x1 1
- (SBO) 0xF 15
- (SBZ) 0x0 0
Branch Pred Enable 0x1 1
L1 ICache Enable 0x1 1
High Vectors 0x0 0
Round Robin 0x0 0
- (SBZ) 0x0 0
- (SBO) 0x1 1
MPU background reg 0x0 0
- (SBO) 0x1 1
Div0 exception 0x0 0
- (SBZ) 0x0 0
FIQ Enable 0x0 0
- (SBO) 0x3 3
VIC 0x0 0
CPSR E bit 0x0 0
- (SBZ) 0x0 0
NMFI 0x1 1
TRE 0x0 0
AFE 0x0 0
Thumb exceptions 0x1 1
Big endian 0x0 0
ACTLR 0x00000045
(raw value) 0x45 69
ACTLR2 0x00000201
(raw value) 0x201 513
CPACR 0xC0000000
(raw value) 0xC0000000 -1073741824
DBGDIDR 0x35137041
Revision 0x1 1
Variant 0x4 4
- (RAZ) 0x70 112
Version 0x3 3 [v7 full]
Context 0x1 1 [2]
BRP 0x5 5 [6]
WRP 0x3 3 [4]
DBGDRAR 0x00000000
Valid 0x0 0
- (UNK) 0x0 0
Address 0x0 0 [0x00000000]
DBGDSAR 0x00030000
Valid 0x0 0
- (UNK) 0x0 0
Address 0x30 48 [0x00030000]
DBGDSCR 0x03000002
HALTED 0x0 0
RESTARTED 0x1 1
MOE 0x0 0
SDABORT_l 0x0 0
ADABORT_l 0x0 0
UND_l 0x0 0
FS 0x0 0
DBGack 0x0 0
INTdis 0x0 0
UDCCdis 0x0 0
ITRen 0x0 0
HDBGen 0x0 0
MDBGen 0x0 0
SPIDdis 0x0 0
SPNIDdis 0x0 0
NS 0x0 0
ADAdiscard 0x0 0
ExtDCCmode 0x0 0
- (SBZ) 0x0 0
InstrCompl_l 0x1 1
PipeAdv 0x1 1
TXfull_l 0x0 0
RXfull_l 0x0 0
- (SBZ) 0x0 0
TXfull 0x0 0
RXfull 0x0 0
- (SBZ) 0x0 0
From M50 / SX70:
CHDK CPU info for 0x412 M50 / 0x805 SX70
------------------------------
ID 0x414FC091
Revision 0x1 1
Part 0xC09 3081
ARM Arch 0xF 15
Variant 0x4 4
Implementor 0x41 65
Cache type 0x83338003
Icache min words/line 0x3 3 [8]
(zero) 0x0 0
L1 Icache policy 0x2 2
Dcache min words/line 0x3 3 [8]
Exclusives Reservation Granule 0x3 3 [8]
Cache Writeback Granule 0x3 3 [8]
(zero) 0x0 0
(register format) 0x4 4
TCM type 0x00000000
(raw value) 0x0 0
MPU type 0x414FC091
S 0x1 1
- 0x48 72
Num of MPU regions 0xC0 192
Multiprocessor ID 0x80000000
(raw value) 0x80000000 -2147483648
Processor feature 0 0x00001231
ARM inst set 0x1 1
Thumb inst set 0x3 3
Jazelle inst set 0x2 2
ThumbEE inst set 0x1 1
- 0x0 0
Processor feature 1 0x00000011
Programmers' model 0x1 1
Security extensions 0x1 1
Microcontr. prog model 0x0 0
- 0x0 0
Debug feature 0x00010444
(raw value) 0x10444 66628
Aux feature 0x00000000
(raw value) 0x0 0
Mem model feature 0 0x00100103
VMSA support 0x3 3
PMSA support 0x0 0
Cache coherence 0x1 1
Outer shareable 0x0 0
TCM support 0x0 0
Auxiliary registers 0x1 1
FCSE support 0x0 0
- 0x0 0
Mem model feature 1 0x20000000
L1 Harvard cache VA 0x0 0
L1 unified cache VA 0x0 0
L1 Harvard cache s/w 0x0 0
L1 unified cache s/w 0x0 0
L1 Harvard cache 0x0 0
L1 unified cache 0x0 0
L1 cache test & clean 0x0 0
Branch predictor 0x2 2
Mem model feature 2 0x01230000
L1 Harvard fg prefetch 0x0 0
L1 Harvard bg prefetch 0x0 0
L1 Harvard range 0x0 0
Harvard TLB 0x0 0
Unified TLB 0x3 3
Mem barrier 0x2 2
WFI stall 0x1 1
HW access flag 0x0 0
Mem model feature 3 0x00102111
Cache maintain MVA 0x1 1
Cache maintain s/w 0x1 1
BP maintain 0x1 1
- 0x102 258
Supersection support 0x0 0
ISA feature 0 0x00101111
Swap instrs 0x1 1
Bitcount instrs 0x1 1
Bitfield instrs 0x1 1
CmpBranch instrs 0x1 1
Coproc instrs 0x0 0
Debug instrs 0x1 1
Divide instrs 0x0 0
- 0x0 0
ISA feature 1 0x13112111
Endian instrs 0x1 1
Exception instrs 0x1 1
Exception AR instrs 0x1 1
Extend instrs 0x2 2
IfThen instrs 0x1 1
Immediate instrs 0x1 1
Interwork instrs 0x3 3
Jazelle instrs 0x1 1
ISA feature 2 0x21232041
LoadStore instrs 0x1 1
Memhint instrs 0x4 4
MultiAccess Interruptible instructions 0x0 0
Mult instrs 0x2 2
MultS instrs 0x3 3
MultU instrs 0x2 2
PSR AR instrs 0x1 1
Reversal instrs 0x2 2
ISA feature 3 0x11112131
Saturate instrs 0x1 1
SIMD instrs 0x3 3
SVC instrs 0x1 1
SynchPrim instrs 0x2 2
TabBranch instrs 0x1 1
ThumbCopy instrs 0x1 1
TrueNOP instrs 0x1 1
T2 Exec Env instrs 0x1 1
ISA feature 4 0x00011142
Unprivileged instrs 0x2 2
WithShifts instrs 0x4 4
Writeback instrs 0x1 1
SMC instrs 0x1 1
Barrier instrs 0x1 1
SynchPrim_instrs_frac 0x0 0
PSR_M instrs 0x0 0
- 0x0 0
ISA feature 5 0x00000000
- 0x0 0
Cache level ID 0x09200003
Cache type, level1 0x3 3 [Separate Icache, Dcache]
Cache type, level2 0x0 0 [no cache]
Cache type, level3 0x0 0 [no cache]
Cache type, level4 0x0 0 [no cache]
Cache type, level5 0x0 0 [no cache]
Cache type, level6 0x0 0 [no cache]
Cache type, level7 0x0 0 [no cache]
Cache type, level8 0x1 1 [Icache only]
Level of coherency 0x1 1
Level of unification 0x1 1
(zero) 0x0 0
Cache size ID reg (data, level0) 0x700FE019
Line size in words 0x1 1 [8]
Associativity 0x3 3 [4]
Number of sets 0x7F 127 [128]
Write allocation 0x1 1
Read allocation 0x1 1
Write back 0x1 1
Write through 0x0 0
Cache size ID reg (inst, level0) 0x200FE019
Line size in words 0x1 1 [8]
Associativity 0x3 3 [4]
Number of sets 0x7F 127 [128]
Write allocation 0x0 0
Read allocation 0x1 1
Write back 0x0 0
Write through 0x0 0
SCTLR 0x40C5187D
MPU Enable 0x1 1
Strict Align 0x0 0
L1 DCache Enable 0x1 1
- (SBO) 0xF 15
- (SBZ) 0x0 0
Branch Pred Enable 0x1 1
L1 ICache Enable 0x1 1
High Vectors 0x0 0
Round Robin 0x0 0
- (SBZ) 0x0 0
- (SBO) 0x1 1
MPU background reg 0x0 0
- (SBO) 0x1 1
Div0 exception 0x0 0
- (SBZ) 0x0 0
FIQ Enable 0x0 0
- (SBO) 0x3 3
VIC 0x0 0
CPSR E bit 0x0 0
- (SBZ) 0x0 0
NMFI 0x0 0
TRE 0x0 0
AFE 0x0 0
Thumb exceptions 0x1 1
Big endian 0x0 0
ACTLR 0x00000045
(raw value) 0x45 69
ACTLR2 0x00000701
(raw value) 0x701 1793
CPACR 0xC0000000
(raw value) 0xC0000000 -1073741824
DBGDIDR 0x35137041
Revision 0x1 1
Variant 0x4 4
- (RAZ) 0x70 112
Version 0x3 3 [v7 full]
Context 0x1 1 [2]
BRP 0x5 5 [6]
WRP 0x3 3 [4]
DBGDRAR 0x00000000
Valid 0x0 0
- (UNK) 0x0 0
Address 0x0 0 [0x00000000]
DBGDSAR 0x00030000
Valid 0x0 0
- (UNK) 0x0 0
Address 0x30 48 [0x00030000]
DBGDSCR 0x03000002
HALTED 0x0 0
RESTARTED 0x1 1
MOE 0x0 0
SDABORT_l 0x0 0
ADABORT_l 0x0 0
UND_l 0x0 0
FS 0x0 0
DBGack 0x0 0
INTdis 0x0 0
UDCCdis 0x0 0
ITRen 0x0 0
HDBGen 0x0 0
MDBGen 0x0 0
SPIDdis 0x0 0
SPNIDdis 0x0 0
NS 0x0 0
ADAdiscard 0x0 0
ExtDCCmode 0x0 0
- (SBZ) 0x0 0
InstrCompl_l 0x1 1
PipeAdv 0x1 1
TXfull_l 0x0 0
RXfull_l 0x0 0
- (SBZ) 0x0 0
TXfull 0x0 0
RXfull 0x0 0
- (SBZ) 0x0 0
Most of the info from the logs in this thread
was integrated in the emulator. If you run the autoexec.bin from this post in QEMU, you should get very similar logs. There will be a few minor differences, but fixing them is more difficult than "just" declaring some constants.