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Messages - names_are_hard

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1
HDR and Dual ISO Postprocessing / Re: trouble building cr2hdr
« on: October 18, 2020, 05:41:15 PM »
Bitbucket removed all Mercurial / Hg repositories.  You'll need to update any references to point to Hetpapod: https://foss.heptapod.net/magic-lantern/magic-lantern

I also see a problem due to python2 dependencies.  You'll need to ensure "python2" points to a valid binary, or fix the scripts some other way.

2
Please tell us which patch you are referring to.

3
Interesting.  The task consumer function on 200D will assign tasks that have that field set to 0xff.  Either CPU will take them.  It's an explicit check "if -1, assign task to this CPU", so it must be deliberate.  I haven't logged any tasks being created that match.

Curious about SMP.  200D says 2.3, release #0059 - a later release but not listed as SMP, yet the hardware is.

4
I thought that might be the case. The "normal" CreateTask (task_create in ML land) doesn't have a CPU argument and looks to copy the CPU index from current_task, so it will always schedule on the same CPU as the running task.

Do you know if existing code ever uses 0xff for cpu_requested?  I'm wondering if/when Canon would want tasks to be scheduled opportunistically on either CPU.

5
Minor update, another field probably identified, better names chosen:
Code: [Select]
        uint8_t         yieldRequest;   // 0x4b, 1
        uint8_t             unknown_0c; // 0x4c, 1
        uint8_t         sleepReason;    // 0x4d, 1
        uint8_t             unknown_0d; // 0x4e, 1
        uint8_t             unknown_0e; // 0x4f, 1
        uint8_t         cpu_requested; // 0x50, 1 : 0, 1, ff,  ff means "any cpu"
        uint8_t         cpu_assigned; // 0x51, 1 : 0, 1, ff, ff means "not yet assigned"
        uint8_t             unknown_11; // 0x52, 1
        uint8_t             unknown_12; // 0x53, 1
        struct context *context;        // 0x54, 4
        uint32_t            unknown_13; // 0x58, 4

6
I think I have found something significant for DIGIC 7 (and probably 8, 10, maybe 6).  The task struct now has a field that determines which CPU the task is scheduled for.

The old struct looks like this for Digic < 7 (only the end shown):
Code: [Select]
        uint8_t         yieldRequest;   // 0x47, 1
        uint8_t             unknown_0c; // 0x48, 1
        uint8_t         sleepReason;    // 0x49, 1
        uint8_t             unknown_0d; // 0x4a, 1
        uint8_t             unknown_0e; // 0x4b, 1
        struct context *context;        // 0x4c, 4

For 200D (probably all D7), I think it looks like this:
Code: [Select]
        uint8_t         yieldRequest;   // 0x4b, 1
        uint8_t             unknown_0c; // 0x4c, 1
        uint8_t         sleepReason;    // 0x4d, 1
        uint8_t             unknown_0d; // 0x4e, 1
        uint8_t             unknown_0e; // 0x4f, 1
        uint8_t         cpu; // 0x50, 1
        uint8_t             unknown_10; // 0x51, 1
        uint8_t             unknown_11; // 0x52, 1
        uint8_t             unknown_12; // 0x53, 1
        struct context *context;        // 0x54, 4
        uint32_t            unknown_13; // 0x58, 4

Trying to update Qemu for 200D, it was failing to reach code that would initialise needed structures in memory.  A task was getting scheduled to do the init, but never running.  It was being scheduled for cpu1, which we disable in Qemu early on.

Forcing cpu = 0 for all tasks, I see the "init1" task running and the structures getting at least partially populated.  Unfortunately it triggers an exception, but before it would never run at all.  It looks to me that there are two init routines, designed to run in parallel (presumably no dependencies?).  See 0xe0040224 and 0xe0040220.  The former is "init", the latter "init1".

Beyond helping with qemu, this may allow ML to choose which cpu tasks run on - and that could mean we can run things twice as fast, if we're cpu bound.  Are we cpu bound for recording video, for example?

7
Camera-specific discussion / Re: Canon EOS R / RP
« on: October 07, 2020, 01:03:17 AM »
Early, 1% perhaps.  There is no real way to tell.  This is a puzzle game, you don't know how many levels there are, and you don't know if one of the levels will be a puzzle that is too hard for you to solve.

8
Camera-specific discussion / Re: Canon EOS R / RP
« on: October 06, 2020, 10:17:50 PM »
You could certainly get Basic to do pretty much anything, but for anything complicated it's harder than C (anything where Basic doesn't have a function already given to you).  For simple stuff, if you don't want menus, or maybe even keys, possibly Basic would be easier.  But which tasks are simpler?  That's not easy to tell in advance.

Additionally, time spent making things work in Basic doesn't progress ML at all.  And, it's a different language, that most of the ML devs won't have used before, so they have to learn it first.  If it's the same devs working on it, it takes time away from ML dev, so it's a tradeoff.  If you want to learn Canon Basic and work on it, that would be great!  There's a lot you can do with it and CHDK documents some of it, with examples.

9
Camera Emergency Department / Re: T5i button operation broken
« on: October 01, 2020, 06:02:45 PM »
Hurrah!  Just a dirty switch - really happy you found a fix :)

10
Camera Emergency Department / Re: T5i button operation broken
« on: September 25, 2020, 08:53:49 PM »
Realistically, you can't use these logs to troubleshoot.  We wanted to see them so that someone who understands them well can look at them.  I skimmed them.  No very obvious errors jumped out.

The most likely thing is that the physical button is broken and this is nothing to do with ML.  What happens if you use a completely empty card, does the button work?  If it doesn't, it's probably the button itself that is broken.  If the button works with an empty card, but doesn't work with an ML card, then it might be ML.

11
Magic Lantern Forum and Site Discussion / Re: A Magic Lantern Discord?
« on: September 25, 2020, 08:38:36 PM »
I don't trust Discord for archiving, and the search functionality is a bit lacking generally.  I view it as very useful for discussion, forming ad-hoc rooms, sharing photos etc.  Not that useful for recording progress.

I think it works well if, when important progress is made, it's recorded on this forum, in code repos, or the wiki.  Then it doesn't get lost if Discord changes terms or gets bought out.

12
General Development Discussion / Re: A question for the C gurus
« on: September 19, 2020, 09:23:04 AM »
@garry23 - yup, you will need to work through some problems to get a working build environment.  But you only have to do that once.  This is doubly true if you do it inside a VM; should you break the environment, you can roll-back the VM (and then update the ML repo).  That's what I was offering to help with - fixing the problems.

I don't have a Mac or Windows, so I can't create the guide you want.  I did make a fully automated way to build ML, using Docker, but there was no interest in it so I didn't get it working well.  This could be improved.  There are significant tradeoffs to doing builds via Docker, but it's theoretically cross platform and handles making a working build environment for you.

ML build via Docker thread:
https://www.magiclantern.fm/forum/index.php?topic=24619.0

14
Camera Emergency Department / Re: T5i button operation broken
« on: September 18, 2020, 02:41:04 AM »
You could put them on pastebin.

15
General Development Discussion / Re: A question for the C gurus
« on: September 18, 2020, 12:27:29 AM »
Compiling ML?  That's pretty easy.  Pop in the Discord and I can walk you through it if you want.  Or there are guides on the forums.

16
General Development Discussion / Re: A question for the C gurus
« on: September 17, 2020, 09:46:25 PM »
Sorry!  It's not much C, so you could learn it if you have the time.

17
General Development Discussion / Re: A question for the C gurus
« on: September 17, 2020, 07:21:49 PM »
You definitely can't read raw_ev because the scope is wrong.  You could make relatively small changes to the ML source to fix the scope, although this is a bad idea (it would get very messy if you want to expose more than a few variables).  A better approach would be a function like get_raw_ev(), and make that do the work, while being visible to Lua.

From some quick reading I don't think you can access C variables directly from Lua even if they're externally visible, because Lua uses a stack abstraction to safely pass data between the two languages.

Not a Lua expert so could be wrong about the details.

18
It's a volunteer project.  People work on whatever they find fun or interesting, or on whatever cam they have.

19
Great!  Added R6 and RP to thread.

I stole your bit twiddling fix and made a repo with my standalone tool.  Tested on Linux, should be portable with minimal changes if anyone needs it.
https://github.com/reticulatedpines/cpuinfo_linux

Yours and mine produce identical output for R6 and RP.

20
Canon RP:

Code: [Select]
ID         0x414FC091
  Revision             0x1 1
  Part                 0xC09 3081
  ARM Arch             0xF 15
  Variant              0x4 4
  Implementor          0x41 65
Cache type 0x83338003
  Icache min words/line 0x3 3 [8]
  (zero)               0x0 0
  L1 Icache policy     0x2 2
  Dcache min words/line 0x3 3 [8]
  Exclusives Reservation Granule 0x3 3 [8]
  Cache Writeback Granule 0x3 3 [8]
  (zero)               0x0 0
  (register format)    0x4 4
TCM type   0x00000000
  (raw value)          0x0 0
TLB type   0x00000404
  TLB                  0x0 0 [Unified TLB]
  TLB entries          0x2 2 [256]
  -                    0x0 0
  Lockable unified or data entries 0x4 4
  Lockable instruction entries 0x0 0
  (zero)               0x0 0
TTBCR      0x00000007
  N                    0x7 7 [TTBR0 table size 128 bytes]
  (zero)               0x0 0
  TTBR0 walks disabled 0x0 0
  TTBR1 walks disabled 0x0 0
  (zero)               0x0 0
  Long descriptors     0x0 0
TTBR0      0xE0004800
  IRGN[1]              0x0 0
  Shareable            0x0 0
  (impl. defined)      0x0 0
  RGN (Outer cacheability) 0x0 0
  NOS (Inner shareable) 0x0 0
  IRGN[0]              0x0 0
  Table address        0x1C00090 29360272 [0xe0004800]
TTBR1      0xE0000000
  IRGN[1]              0x0 0
  Shareable            0x0 0
  (impl. defined)      0x0 0
  RGN (Outer cacheability) 0x0 0
  NOS (Inner shareable) 0x0 0
  IRGN[0]              0x0 0
  Table address        0x1C00000 29360128 [0xe0000000]
Multiprocessor ID 0x80000000
  (raw value)          0x80000000 -2147483648
Revision ID 0x00000000
  (raw value)          0x0 0
Processor feature 0 0x00001231
  ARM inst set         0x1 1
  Thumb inst set       0x3 3
  Jazelle inst set     0x2 2
  ThumbEE inst set     0x1 1
  -                    0x0 0
Processor feature 1 0x00000011
  Programmers' model   0x1 1
  Security extensions  0x1 1
  Microcontr. prog model 0x0 0
  Virt. extensions     0x0 0
  Generic timer ext.   0x0 0
  -                    0x0 0
Debug feature 0x00010444
  Coproc. dbg model    0x4 4
  Coproc. secure dbg model 0x4 4
  Memory-mapped dbg model 0x4 4
  Coproc. trace model  0x0 0
  Memory-mapped trace model 0x1 1
  Debug model M        0x0 0
  Perf. monitors       0x0 0
  -                    0x0 0
Aux feature 0x00000000
  (raw value)          0x0 0
Mem model feature 0 0x00100103
  VMSA support         0x3 3
  PMSA support         0x0 0
  Cache coherence      0x1 1
  Outer shareable      0x0 0
  TCM support          0x0 0
  Auxiliary registers  0x1 1
  FCSE support         0x0 0
  -                    0x0 0
Mem model feature 1 0x20000000
  L1 Harvard cache VA  0x0 0
  L1 unified cache VA  0x0 0
  L1 Harvard cache s/w 0x0 0
  L1 unified cache s/w 0x0 0
  L1 Harvard cache     0x0 0
  L1 unified cache     0x0 0
  L1 cache test & clean 0x0 0
  Branch predictor     0x2 2
Mem model feature 2 0x01230000
  L1 Harvard fg prefetch 0x0 0
  L1 Harvard bg prefetch 0x0 0
  L1 Harvard range     0x0 0
  Harvard TLB          0x0 0
  Unified TLB          0x3 3
  Mem barrier          0x2 2
  WFI stall            0x1 1
  HW access flag       0x0 0
Mem model feature 3 0x00102111
  Cache maintain MVA   0x1 1 [Supported]
  Cache maintain set/way 0x1 1 [Supported]
  Branch predictor maintenance 0x1 1 [Invalidate all]
  Maintenance broadcast 0x2 2
  -                    0x0 0
  Transl. table coherent walk 0x1 1
  Cached memory size   0x0 0 [4 GByte]
  Supersection support 0x0 0 [Supported]
ISA feature 0 0x00101111
  Swap instrs          0x1 1
  Bitcount instrs      0x1 1
  Bitfield instrs      0x1 1
  CmpBranch instrs     0x1 1
  Coproc instrs        0x0 0
  Debug instrs         0x1 1
  Divide instrs        0x0 0
  -                    0x0 0
ISA feature 1 0x13112111
  Endian instrs        0x1 1
  Exception instrs     0x1 1
  Exception AR instrs  0x1 1
  Extend instrs        0x2 2
  IfThen instrs        0x1 1
  Immediate instrs     0x1 1
  Interwork instrs     0x3 3
  Jazelle instrs       0x1 1
ISA feature 2 0x21232041
  LoadStore instrs     0x1 1
  Memhint instrs       0x4 4
  MultiAccess Interruptible instructions 0x0 0
  Mult instrs          0x2 2
  MultS instrs         0x3 3
  MultU instrs         0x2 2
  PSR AR instrs        0x1 1
  Reversal instrs      0x2 2
ISA feature 3 0x11112131
  Saturate instrs      0x1 1
  SIMD instrs          0x3 3
  SVC instrs           0x1 1
  SynchPrim instrs     0x2 2
  TabBranch instrs     0x1 1
  ThumbCopy instrs     0x1 1
  TrueNOP instrs       0x1 1
  T2 Exec Env instrs   0x1 1
ISA feature 4 0x00011142
  Unprivileged instrs  0x2 2
  WithShifts instrs    0x4 4
  Writeback instrs     0x1 1
  SMC instrs           0x1 1
  Barrier instrs       0x1 1
  SynchPrim_instrs_frac 0x0 0
  PSR_M instrs         0x0 0
  -                    0x0 0
ISA feature 5 0x00000000
  -                    0x0 0
Cache level ID 0x09200003
  Cache type, level1   0x3 3 [Separate Icache, Dcache]
  Cache type, level2   0x0 0 [no cache]
  Cache type, level3   0x0 0 [no cache]
  Cache type, level4   0x0 0 [no cache]
  Cache type, level5   0x0 0 [no cache]
  Cache type, level6   0x0 0 [no cache]
  Cache type, level7   0x0 0 [no cache]
  Level of unification Inner Shareable 0x1 1
  Level of coherency   0x1 1
  Level of unification 0x1 1
  (zero)               0x0 0
Cache size ID reg (data, level0) 0x700FE019
  Line size in words   0x1 1 [8]
  Associativity        0x3 3 [4]
  Number of sets       0x7F 127 [128]
  Write allocation     0x1 1
  Read allocation      0x1 1
  Write back           0x1 1
  Write through        0x0 0
Cache size ID reg (inst, level0) 0x200FE019
  Line size in words   0x1 1 [8]
  Associativity        0x3 3 [4]
  Number of sets       0x7F 127 [128]
  Write allocation     0x0 0
  Read allocation      0x1 1
  Write back           0x0 0
  Write through        0x0 0
SCTLR      0x40C5187D
  MMU Enable           0x1 1
  Strict Align         0x0 0
  Data or Unified Cache Enable 0x1 1
  CP15 Barrier Enable  0x1 1
  - (SBO)              0x7 7
  - (SBZ)              0x0 0
  SWP/SWPB Enable      0x0 0
  Branch Pred Enable   0x1 1
  ICache Enable        0x1 1
  High Vector          0x0 0
  Round Robin          0x0 0
  - (SBZ)              0x0 0
  - (SBO)              0x1 1
  HA flag              0x0 0
  - (SBO)              0x1 1
  WXN (virt. ext. only) 0x0 0
  UWXN (virt. ext. only) 0x0 0
  FIQ Enable           0x0 0
  - (SBO)              0x3 3
  VE                   0x0 0
  CPSR E               0x0 0
  - (SBZ)              0x0 0
  NMFI                 0x0 0
  TRE                  0x0 0
  AFE                  0x0 0
  Thumb exceptions     0x1 1
  - (SBZ)              0x0 0
ACTLR      0x00000045
  Cache & TLB maint. broadcast 0x1 1
  L2 prefetch enable   0x0 0
  L1 prefetch enable   0x1 1
  Write full line of zeroes 0x0 0
  (zero)               0x0 0
  SMP                  0x1 1
  Exclusive cache      0x0 0
  Alloc in one way     0x0 0
  Parity on            0x0 0
  -                    0x0 0
ACTLR2     0x00000701
  (raw value)          0x701 1793
CPACR      0xC0000000
  (zero)               0x0 0
  CP10 access permission 0x0 0
  CP11 access permission 0x0 0
  (zero)               0x0 0
  D32DIS               0x1 1
  ASEDIS               0x1 1
DACR       0x0000C000
  (raw value)          0xC000 49152
NSACR (sec. ext. only) 0x55555555
  (raw value)          0x55555555 1431655765
DBGDIDR    0x35137041
  Revision             0x1 1
  Variant              0x4 4
  - (RAZ)              0x70 112
  Version              0x3 3 [v7 full]
  Context              0x1 1 [2]
  BRP                  0x5 5 [6]
  WRP                  0x3 3 [4]
DBGDRAR    0x00000000
  Valid                0x0 0
  - (UNK)              0x0 0
  Address              0x0 0 [0x00000000]
DBGDSAR    0x00030000
  Valid                0x0 0
  - (UNK)              0x0 0
  Address              0x30 48 [0x00030000]
DBGDSCR    0x03000002
  HALTED               0x0 0
  RESTARTED            0x1 1
  MOE                  0x0 0
  SDABORT_l            0x0 0
  ADABORT_l            0x0 0
  UND_l                0x0 0
  FS                   0x0 0
  DBGack               0x0 0
  INTdis               0x0 0
  UDCCdis              0x0 0
  ITRen                0x0 0
  HDBGen               0x0 0
  MDBGen               0x0 0
  SPIDdis              0x0 0
  SPNIDdis             0x0 0
  NS                   0x0 0
  ADAdiscard           0x0 0
  ExtDCCmode           0x0 0
  - (SBZ)              0x0 0
  InstrCompl_l         0x1 1
  PipeAdv              0x1 1
  TXfull_l             0x0 0
  RXfull_l             0x0 0
  - (SBZ)              0x0 0
  TXfull               0x0 0
  RXfull               0x0 0
  - (SBZ)              0x0 0
Config base addr reg 0xC1000000
  (raw value)          0xC1000000 -1056964608
PLEIDR     0x00000000
  (raw value)          0x0 0
TLB lockdown reg 0x00000000
  (raw value)          0x0 0
PRRR       0x00098AA4
  (raw value)          0x98AA4 625316
NMRR       0x44E048E0
  (raw value)          0x44E048E0 1155549408

21
Canon R6:

Code: [Select]
ID         0x414FC091
  Revision             0x1 1
  Part                 0xC09 3081
  ARM Arch             0xF 15
  Variant              0x4 4
  Implementor          0x41 65
Cache type 0x83338003
  Icache min words/line 0x3 3 [8]
  (zero)               0x0 0
  L1 Icache policy     0x2 2
  Dcache min words/line 0x3 3 [8]
  Exclusives Reservation Granule 0x3 3 [8]
  Cache Writeback Granule 0x3 3 [8]
  (zero)               0x0 0
  (register format)    0x4 4
TCM type   0x00000000
  (raw value)          0x0 0
TLB type   0x00000404
  TLB                  0x0 0 [Unified TLB]
  TLB entries          0x2 2 [256]
  -                    0x0 0
  Lockable unified or data entries 0x4 4
  Lockable instruction entries 0x0 0
  (zero)               0x0 0
TTBCR      0x00000007
  N                    0x7 7 [TTBR0 table size 128 bytes]
  (zero)               0x0 0
  TTBR0 walks disabled 0x0 0
  TTBR1 walks disabled 0x0 0
  (zero)               0x0 0
  Long descriptors     0x0 0
TTBR0      0xDFFC4800
  IRGN[1]              0x0 0
  Shareable            0x0 0
  (impl. defined)      0x0 0
  RGN (Outer cacheability) 0x0 0
  NOS (Inner shareable) 0x0 0
  IRGN[0]              0x0 0
  Table address        0x1BFF890 29358224 [0xdffc4800]
TTBR1      0xDFFC0000
  IRGN[1]              0x0 0
  Shareable            0x0 0
  (impl. defined)      0x0 0
  RGN (Outer cacheability) 0x0 0
  NOS (Inner shareable) 0x0 0
  IRGN[0]              0x0 0
  Table address        0x1BFF800 29358080 [0xdffc0000]
Multiprocessor ID 0x80000000
  (raw value)          0x80000000 -2147483648
Revision ID 0x00000000
  (raw value)          0x0 0
Processor feature 0 0x00001231
  ARM inst set         0x1 1
  Thumb inst set       0x3 3
  Jazelle inst set     0x2 2
  ThumbEE inst set     0x1 1
  -                    0x0 0
Processor feature 1 0x00000011
  Programmers' model   0x1 1
  Security extensions  0x1 1
  Microcontr. prog model 0x0 0
  Virt. extensions     0x0 0
  Generic timer ext.   0x0 0
  -                    0x0 0
Debug feature 0x00010444
  Coproc. dbg model    0x4 4
  Coproc. secure dbg model 0x4 4
  Memory-mapped dbg model 0x4 4
  Coproc. trace model  0x0 0
  Memory-mapped trace model 0x1 1
  Debug model M        0x0 0
  Perf. monitors       0x0 0
  -                    0x0 0
Aux feature 0x00000000
  (raw value)          0x0 0
Mem model feature 0 0x00100103
  VMSA support         0x3 3
  PMSA support         0x0 0
  Cache coherence      0x1 1
  Outer shareable      0x0 0
  TCM support          0x0 0
  Auxiliary registers  0x1 1
  FCSE support         0x0 0
  -                    0x0 0
Mem model feature 1 0x20000000
  L1 Harvard cache VA  0x0 0
  L1 unified cache VA  0x0 0
  L1 Harvard cache s/w 0x0 0
  L1 unified cache s/w 0x0 0
  L1 Harvard cache     0x0 0
  L1 unified cache     0x0 0
  L1 cache test & clean 0x0 0
  Branch predictor     0x2 2
Mem model feature 2 0x01230000
  L1 Harvard fg prefetch 0x0 0
  L1 Harvard bg prefetch 0x0 0
  L1 Harvard range     0x0 0
  Harvard TLB          0x0 0
  Unified TLB          0x3 3
  Mem barrier          0x2 2
  WFI stall            0x1 1
  HW access flag       0x0 0
Mem model feature 3 0x00102111
  Cache maintain MVA   0x1 1 [Supported]
  Cache maintain set/way 0x1 1 [Supported]
  Branch predictor maintenance 0x1 1 [Invalidate all]
  Maintenance broadcast 0x2 2
  -                    0x0 0
  Transl. table coherent walk 0x1 1
  Cached memory size   0x0 0 [4 GByte]
  Supersection support 0x0 0 [Supported]
ISA feature 0 0x00101111
  Swap instrs          0x1 1
  Bitcount instrs      0x1 1
  Bitfield instrs      0x1 1
  CmpBranch instrs     0x1 1
  Coproc instrs        0x0 0
  Debug instrs         0x1 1
  Divide instrs        0x0 0
  -                    0x0 0
ISA feature 1 0x13112111
  Endian instrs        0x1 1
  Exception instrs     0x1 1
  Exception AR instrs  0x1 1
  Extend instrs        0x2 2
  IfThen instrs        0x1 1
  Immediate instrs     0x1 1
  Interwork instrs     0x3 3
  Jazelle instrs       0x1 1
ISA feature 2 0x21232041
  LoadStore instrs     0x1 1
  Memhint instrs       0x4 4
  MultiAccess Interruptible instructions 0x0 0
  Mult instrs          0x2 2
  MultS instrs         0x3 3
  MultU instrs         0x2 2
  PSR AR instrs        0x1 1
  Reversal instrs      0x2 2
ISA feature 3 0x11112131
  Saturate instrs      0x1 1
  SIMD instrs          0x3 3
  SVC instrs           0x1 1
  SynchPrim instrs     0x2 2
  TabBranch instrs     0x1 1
  ThumbCopy instrs     0x1 1
  TrueNOP instrs       0x1 1
  T2 Exec Env instrs   0x1 1
ISA feature 4 0x00011142
  Unprivileged instrs  0x2 2
  WithShifts instrs    0x4 4
  Writeback instrs     0x1 1
  SMC instrs           0x1 1
  Barrier instrs       0x1 1
  SynchPrim_instrs_frac 0x0 0
  PSR_M instrs         0x0 0
  -                    0x0 0
ISA feature 5 0x00000000
  -                    0x0 0
Cache level ID 0x09200003
  Cache type, level1   0x3 3 [Separate Icache, Dcache]
  Cache type, level2   0x0 0 [no cache]
  Cache type, level3   0x0 0 [no cache]
  Cache type, level4   0x0 0 [no cache]
  Cache type, level5   0x0 0 [no cache]
  Cache type, level6   0x0 0 [no cache]
  Cache type, level7   0x0 0 [no cache]
  Level of unification Inner Shareable 0x1 1
  Level of coherency   0x1 1
  Level of unification 0x1 1
  (zero)               0x0 0
Cache size ID reg (data, level0) 0x700FE019
  Line size in words   0x1 1 [8]
  Associativity        0x3 3 [4]
  Number of sets       0x7F 127 [128]
  Write allocation     0x1 1
  Read allocation      0x1 1
  Write back           0x1 1
  Write through        0x0 0
Cache size ID reg (inst, level0) 0x201FE019
  Line size in words   0x1 1 [8]
  Associativity        0x3 3 [4]
  Number of sets       0xFF 255 [256]
  Write allocation     0x0 0
  Read allocation      0x1 1
  Write back           0x0 0
  Write through        0x0 0
SCTLR      0x40C5187D
  MMU Enable           0x1 1
  Strict Align         0x0 0
  Data or Unified Cache Enable 0x1 1
  CP15 Barrier Enable  0x1 1
  - (SBO)              0x7 7
  - (SBZ)              0x0 0
  SWP/SWPB Enable      0x0 0
  Branch Pred Enable   0x1 1
  ICache Enable        0x1 1
  High Vector          0x0 0
  Round Robin          0x0 0
  - (SBZ)              0x0 0
  - (SBO)              0x1 1
  HA flag              0x0 0
  - (SBO)              0x1 1
  WXN (virt. ext. only) 0x0 0
  UWXN (virt. ext. only) 0x0 0
  FIQ Enable           0x0 0
  - (SBO)              0x3 3
  VE                   0x0 0
  CPSR E               0x0 0
  - (SBZ)              0x0 0
  NMFI                 0x0 0
  TRE                  0x0 0
  AFE                  0x0 0
  Thumb exceptions     0x1 1
  - (SBZ)              0x0 0
ACTLR      0x00000045
  Cache & TLB maint. broadcast 0x1 1
  L2 prefetch enable   0x0 0
  L1 prefetch enable   0x1 1
  Write full line of zeroes 0x0 0
  (zero)               0x0 0
  SMP                  0x1 1
  Exclusive cache      0x0 0
  Alloc in one way     0x0 0
  Parity on            0x0 0
  -                    0x0 0
ACTLR2     0x00000701
  (raw value)          0x701 1793
CPACR      0xC0000000
  (zero)               0x0 0
  CP10 access permission 0x0 0
  CP11 access permission 0x0 0
  (zero)               0x0 0
  D32DIS               0x1 1
  ASEDIS               0x1 1
DACR       0x0000C000
  (raw value)          0xC000 49152
NSACR (sec. ext. only) 0x55555555
  (raw value)          0x55555555 1431655765
DBGDIDR    0x35137041
  Revision             0x1 1
  Variant              0x4 4
  - (RAZ)              0x70 112
  Version              0x3 3 [v7 full]
  Context              0x1 1 [2]
  BRP                  0x5 5 [6]
  WRP                  0x3 3 [4]
DBGDRAR    0x00000000
  Valid                0x0 0
  - (UNK)              0x0 0
  Address              0x0 0 [0x00000000]
DBGDSAR    0x00030000
  Valid                0x0 0
  - (UNK)              0x0 0
  Address              0x30 48 [0x00030000]
DBGDSCR    0x03008002
  HALTED               0x0 0
  RESTARTED            0x1 1
  MOE                  0x0 0
  SDABORT_l            0x0 0
  ADABORT_l            0x0 0
  UND_l                0x0 0
  FS                   0x0 0
  DBGack               0x0 0
  INTdis               0x0 0
  UDCCdis              0x0 0
  ITRen                0x0 0
  HDBGen               0x0 0
  MDBGen               0x1 1
  SPIDdis              0x0 0
  SPNIDdis             0x0 0
  NS                   0x0 0
  ADAdiscard           0x0 0
  ExtDCCmode           0x0 0
  - (SBZ)              0x0 0
  InstrCompl_l         0x1 1
  PipeAdv              0x1 1
  TXfull_l             0x0 0
  RXfull_l             0x0 0
  - (SBZ)              0x0 0
  TXfull               0x0 0
  RXfull               0x0 0
  - (SBZ)              0x0 0
Config base addr reg 0xC1000000
  (raw value)          0xC1000000 -1056964608
PLEIDR     0x00000000
  (raw value)          0x0 0
TLB lockdown reg 0x00000000
  (raw value)          0x0 0
PRRR       0x00098AA4
  (raw value)          0x98AA4 625316
NMRR       0x44E048E0
  (raw value)          0x44E048E0 1155549408

22
I have a crude early port of the cpuinfo parser.  There's some conditional stuff around VMSA, PMSA and v5 / v7 that for now I ignore.  I don't have a good way to check if the output is sensible.  Here's a truncated example:

Code: [Select]
./build/parser cpuinfo.rp.dat && cat CPUINFO.TXT

ID         0x414FC091
  Revision             0x1 1
  Part                 0xC09 3081
  ARM Arch             0xF 15
  Variant              0x4 4
  Implementor          0x41 65
Cache type 0x83338003
  Icache min words/line 0x3 3 [8]
  (zero)               0x0 0
  L1 Icache policy     0x2 2
  Dcache min words/line 0x3 3 [8]
  Exclusives Reservation Granule 0x3 3 [8]
  Cache Writeback Granule 0x3 3 [8]
  (zero)               0x0 0
  (register format)    0x4 4
TCM type   0x00000000
  (raw value)          0x0 0
TLB type   0x00000404
  TLB                  0x0 0 [Unified TLB]
  TLB entries          0x2 2 [256]
  -                    0x0 0
  Lockable unified or data entries 0x4 4
  Lockable instruction entries 0x0 0
  (zero)               0x0 0

Does that look obviously wrong to anybody?

@srsa - can I ignore memmapping_vmsa(), or is it important to get that working?

23
I found stubs for R6, got cpuinfo dumper built.  Thanks to @yourboylloyd who is a brave tester, we can confirm it works.  I'm now porting the code to linux so I can view the results.

24
Camera-specific discussion / Re: Canon EOS R5 / R6
« on: September 12, 2020, 04:38:32 AM »
Could be compression artifacts.  Looks similar to JPEG quantisation.  RAW wouldn't have those.

25
Thanks, this is quite interesting.  Are you aware of Scout debugger?

https://github.com/CheckPointSW/Scout

In theory this can be loaded into Canon cams and act as a network debugger.  I played with it briefly but couldn't work out how to build it.

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