Author Topic: CHDK cpuinfo (portable code, also digic 6)  (Read 12868 times)

a1ex

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CHDK cpuinfo (portable code, also digic 6)
« on: August 17, 2016, 03:51:37 PM »
Since I'm a bit stuck with DIGIC 6, I took the cpuinfo module from CHDK and integrated it with the portable display code. This should give detailed info about the hardware (CPU, caches, memory configuration and so on).

Besides the DIGIC 6 cameras, I'm also interested in the results from recent ports (70D, 100D, 1200D); tests from other cameras are also welcome, but they are mostly for fun.

Source code: the recovery branch

Binaries:
autoexec.bin - for all ML-enabled cameras
CPUI_80D.FIR
CPUI750D.FIR
CPUI760D.FIR
CPUI-7D2.FIR
CPUI1300.FIR (1300D)

This code is pretty verbose - it will show a few pages of low-level info. You will need to take screenshots to be able to read all that stuff.

As I'm on a very slow network connection, please do not upload large screenshots. If possible, it would be best if you could write down the info as plain text. If not, please try to keep the image size small (under 50K each).

DeafEyeJedi

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Re: CHDK cpuinfo (portable code, also digic 6)
« Reply #1 on: August 17, 2016, 06:53:12 PM »
Nice progress @a1ex. Question -- do I also include the autoexec.bin if I were to run the CPUI test on a 7D2 that I can borrow from a co-worker.
5D3.113 • 5D3.123 • EOSM.203 • 7D.203 • 70D.112 • 100D.101

a1ex

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Re: CHDK cpuinfo (portable code, also digic 6)
« Reply #2 on: August 17, 2016, 07:00:40 PM »
No, just the FIR.

nikfreak

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70D.112 & 100D.101

atonal

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Re: CHDK cpuinfo (portable code, also digic 6)
« Reply #4 on: August 17, 2016, 10:57:34 PM »
I did the 7D2. Might contain typos and other mistakes, my screen shots weren't all crystal clear. I can upload the pics somewhere if someone wants to double check any of the data.

Code: [Select]
---------------------------------------------- page 1
CHDK CPU info for 0x289 7D2
-----------------------------
ID              0x411FC143
    Revision                0x3 3
    Part                    0xC14 3092
    ARM Arch                0xF 15
    Variant                 0x1 1
    Implementor             0x41 65
Cache type      0x8003C003
    Icache min words/line   0x3 3 [8]
    (zero)                  0x0 0
    L1 Icache policy        0x3 3
    Dcache min words/line   0x3 3 [8]
    Exclusives Reservation Granule  0x0 0 [no info]
    Cache Writeback Granule 0x0 0 [no info]
    (zero)                  0x0 0
    (register format)       0x4 4
TCM type        0x00010001
    (raw value)             0x10001 65537
MPU type        0x00000800
    S                       0x0 0
    -                       0x0 0
    Num of MPU regions      0x8 8
Processor feature 0 0x00000131
    ARM inst set            0x1 1
    Thumb inst set          0x3 3
    Jazelle inst set        0x1 1
    ThumbEE inst set        0x0 0
    -                       0x0 0
Processor feature 1 0x00000001
    Programmers' model      0x1 1
    Security extensions     0x0 0
    Microcontr, prog model  0x0 0
    -                       0x0 0
Debug feature   0x00010400
    (raw value)             0x10400 66560
Aux feature     0x00000000
    (raw value)             0x0 0
Mem model feature 0 0x00210030
    VMSA support            0x0 0
    PMSA support            0x3 3
    Cache coherence         0x0 0
    Outer shareable         0x0 0
    TCM support             0x1 1
    Auxiliary registers     0x2 2
---------------------------------------------- page 2
    FCSE support            0x0 0
    -                       0x0 0
Mem model feature 1 0x00000000
    L1 Harvard cache VA     0x0 0
    L1 unified cache VA     0x0 0
    L1 Harvard cache s/w    0x0 0
    L1 unified caceh s/w    0x0 0
    L1 Harvard cache        0x0 0
    L1 unified cache        0x0 0
    L1 cache test & clean   0x0 0
    Branch predictor        0x0 0
Mem model feature 2 0x01200000
    L1 Harvard fg prefetch  0x0 0
    L1 Harvard bg prefetch  0x0 0
    Harvar TLB              0x0 0
    Unified TLB             0x0 0
    Mem barrier             0x2 2
    WFI stall               0x1 1
    HW access flag          0x0 0
Mem model feature 3 0x00000011
    Cache maintain MVA      0x1 1
    Cache maintain s/w      0x1 1
    BP maintain             0x0 0
    -                       0x0 0
    Supersection support    0x0 0
ISA feature 0 0x01101111
    Swap instrs             0x1 1
    Bitcount instrs         0x1 1
    Bitfield instrs         0x1 1
    CmpBranch instrs        0x1 1
    Coproc instrs           0x0 0
    Debug instrs            0x1 1
    Divide instrs           0x1 1
    -                       0x0 0
ISA feature 1 0x13112111
    Endian instrs           0x1 1
    Exception instrs        0x1 1
    Exception AR instrs     0x1 1
    Extend instrs           0x2 2
    IfThen instrs           0x1 1
    Immediate instrs        0x1 1
    Interwork instrs        0x3 3
    Jazelle instrs          0x1 1
ISA feature 2 0x21232131
    LoadStore instrs        0x1 1
    Memhint instrs          0x3 3
---------------------------------------------- page 3
    MultiAccess Interruptible instructions 0x1 1
    Mult instrs             0x2 2
    MultS instrs            0x3 3
    MultU instrs            0x2 2
    PSR AR instrs           0x1 1
    Reversal instrs         0x2 2
ISA feature 3 0x01112131
    Saturate instrs         0x1 1
    SIMD instrs             0x3 3
    SVC instrs              0x1 1
    SynchPrim instrs        0x2 2
    TabBranch instrs        0x1 1
    ThumbCopy instrs        0x1 1
    TrueNOP instrs          0x1 1
    T2 Exec Env instrs      0x0 0
ISA feature 4 0x00010142
    Unprivileged instrs     0x2 2
    WithShifts instrs       0x4 4
    Writeback instrs        0x1 1
    SMC instrs              0x0 0
    Barrier instrs          0x1 1
    SynchPrim_instrs_frac   0x0 0
    PSR_M instrs            0x0 0
    -                       0x0 0
ISA feature 5 0x00000000
    -                       0x0 0
Cache level ID 0x09000003
    Cache type, level1      0x3 3 [Separate Icache, Dcache]
    Cache type, level2      0x0 0 [no cache]
    Cache type, level3      0x0 0 [no cache]
    Cache type, level4      0x0 0 [no cache]
    Cache type, level5      0x0 0 [no cache]
    Cache type, level6      0x0 0 [no cache]
    Cache type, level7      0x0 0 [no cache]
    Cache type, level8      0x0 0 [no cache]
    Level of coherency      0x1 1
    Level of unification    0x1 1
    (zero)                  0x0 0
Cache size ID reg (data, level0) 0xF00FE019
    Line size in words      0x1 1 [8]
    Associativity           0x3 3 [4]
    Number of sets          0x7F 127 [128]
    Write allocation        0x1 1
    Read allocation         0x1 1
    Write back              0x1 1
    Write through           0x1 1
Cache size ID reg (inst, level0) 0xF00FE019
---------------------------------------------- page 4
    Line size inf words     0x1 1 [8]
    Associativity           0x3 3 [4]
    Number of sets          0x7F 127 [128]
    Write allocation        0x1 1
    Read allocation         0x1 1
    Write back              0x1 1
    Write through           0x1 1
Build options 1 0x00010000
    (raw value)             0x10000 65536
Build options 2 0x00CFC010
    (raw value)             0xCFC010 13615120
ARCM region reg 0x00000015
    Enabled                 0x1 1
    -                       0x0 0
    Size                    0x5 5 [16K]
    -                       0x0 0
    Base address            0x0 0 [0x00000000]
BTCM region reg 0x0000001D
    Enabled                 0x1 1
    -                       0x0 0
    Size                    0x7 7 [64K]
    -                       0x0 0
    Base address            0x80000 524288 [0x80000000]
MPU region 0 base 0x00000000
    Base address            0x0 0
MPU region 0 size & enable  0x0000003F
    Enabled                 0x1 1
    Size                    0x1F 31 [4G]
    -                       0x0 0
    Sub-regions disabled    0x0 0 [00000000]
MPU region 0 access control 0x00000320
    Region attributes       0x20 32 [Inner Non-cacheable; Outer Non-cacheable; Non-shared]
    -                       0x0 0
    Access permission       0x3 3 [P:RW U:RW]
    -                       0x0 0
    Execute never           0x0 0
MPU region 1 base           0x00000000
    Base address            0x0 0
MPU region 1 size & enable  0x0000003B
    Enabled                 0x1 1
    Size                    0x1D 29 [1G]
    -                       0x0 0
    Sub-regions disabled    0x0 0 [00000000]
MPU region 1 access contro  0x00000329
    Region attributes       0x29 41 [Inner Write-back, write-allocat; Outer Write-back, write-allocate; Non-shared]
---------------------------------------------- page 5
    -                       0x0 0
    Access permission       0x3 3 [P:RW U:RW]
    -                       0x0 0
    Execute never           0x0 0
MPU region 2 base 0xBFE00000
    Base address            0xBFE00000 -1075838976
MPU region 2 size & enable  0x00000029
    Enabled                 0x1 1
    Size                    0x14 20 [2M]
    -                       0x0 0
    Sub-regions disabled    0x0 0 [00000000]
MPU region 2 access control 0x00000324
    Region attributes       0x24 36 [Inner Non-cacheable; Outer Non-cacheable; Shared]
    -                       0x0 0
    Access permission       0x3 3 [P:RW U:RW]
    -                       0x0 0
    Execute never           0x0 0
MPU region 3 base 0xC0000000
    Base address            0xC0000000 -1073741824
MPU region 3 size & enable  0x0000003B
    Enabled                 0x1 1
    Size                    0x1D 29 [1G]
    -                       0x0 0
    Sub-regions disabled    0x0 0 [00000000]
MPU region 3 access control 0x00000305
    Region attributes       0x5 5 [Shareable device; Shareble]
    -                       0x0 0
    Access permission       0x3 3 [P:RW U:RW]
    -                       0x0 0
    Execute never           0x0 0
MPU region 4 base 0xDFE00000
    Base address            0xDFE00000 -538968064
MPU region 4 size & enable  0x00000029
    Enabled                 0x1 1
    Size                    0x14 20 [2M]
    -                       0x0 0
    Sub-regions disabled    0x0 0 [00000000]
MPU region 4 access control 0x00000324
    Region attributes       0x24 36 [Inner Non-cacheable; Outer Non-cacheable; Shared]
    -                       0x0 0
    Access permission       0x3 3 [P:RW U:RW]
    -                       0x0 0
    Execute never           0x0 0
MPU region 5 base 0xEE000000
    Base address            0xEE000000 -301989888
MPU region 5 size & enable  0x00000031
    Enabled                 0x1 1
---------------------------------------------- page 6
    Size                    0x18 24 [32M]
    -                       0x0 0
    Sub-regions disabled    0x0 0 [00000000]
MPU region 5 access control 0x00000329
    Region attributes       0x29 41 [Inner Write-back, write-allocate; Outer Write-back, write-allocate; Non-shared]
    -                       0x0 0
    Access permission       0x3 3 [P:RW U:RW]
    -                       0x0 0
    Execute never           0x0 0
MPU region 6 base 0xFE000000
    Base address            0xFE000000 -33554432
MPU region 6 size & enable 0x00000031
    Enabled                 0x1 1
    Size                    0x18 24 [32M]
    -                       0x0 0
    Sub-regions disabled    0x0 0 [00000000]
MPU region 6 access control 0x00000329
    Region attributes       0x29 41 [Inner Write-back, write-allocate; Outer Write-back, write-allocate; Non-shared]
    -                       0x0 0
    Access permission       0x3 [P:RW U:RW]
    -                       0x0 0
    Execute never           0x0 0
MPU region 7 base 0x00000000
    Base address            0x0 0
MPU region 7 size & enable 0x00000000
    Enabled                 0x0 0
    Size                    0x0 0 [invalid]
    -                       0x0 0
    Sub-regions disabled    0x0 0 [00000000]
MPU region 7 access control 0x00000000
    Region attributes       0x0 0 [Strongly ordered, shareable; ]
    -                       0x0 0
    Access permission       0x0 0 [P:-- U:--]
    -                       0x0 0
    Execute never           0x0 0


JagoUK

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Re: CHDK cpuinfo (portable code, also digic 6)
« Reply #5 on: August 17, 2016, 11:10:27 PM »
Hi A1ex

Here are pictures from my 7DII

It is running FW 1.0.5, let me know if you need me to downgrade.
https://www.dropbox.com/s/9qvn4ap1ckqernq/1.jpg
https://www.dropbox.com/s/rsfd39tuqqwjd2p/2.jpg
https://www.dropbox.com/s/iixu0uegfrdhfl7/3.jpg
https://www.dropbox.com/s/3p5n8c783di6w2e/4.jpg
https://www.dropbox.com/s/y3x0myw8m5nmb9b/5.jpg
https://www.dropbox.com/s/svsygseeoeigv6p/6.jpg

Seems atonal beat me too it, oh well they are there if needed and as stated from 1.0.5 fw,

Chellyandruu

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Re: CHDK cpuinfo (portable code, also digic 6)
« Reply #6 on: August 18, 2016, 06:18:12 PM »
hey ALEX,on the 80d i got the same information  as atonal got on the 7d2.only difference was the first line which read -
CHDK CPU info for 0x350 80d
-----------------------------
ID              0x411FC143.If you need picture proof just tell me.


atonal

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Re: CHDK cpuinfo (portable code, also digic 6)
« Reply #8 on: August 19, 2016, 11:12:27 AM »
A few extra registers that (at least) 7D2 now prints:

Code: [Select]
Multiprocessor ID   0x00000000
SCTLR   0x08E5187D
    (raw value)             0x8E5187D 149231741
ACTLR   0x00000020
    (raw value)             0x20 32
ACTLR2  0x00000000
    (raw value)             0x0 0
CPACR   0x00000000
    (raw value)             0x0 0

a1ex

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Re: CHDK cpuinfo (portable code, also digic 6)
« Reply #9 on: August 19, 2016, 11:55:48 AM »
Thanks folks.

0xC14 should be a Cortex R4, just like CHDK guys already found.

A small bit of mystery: interrupts appear to be done in Thumb mode, so I expect SCTLR.TE (bit 30) to be 1...

edit: mystery solved
Code: [Select]
[CPU0] FE0A0070: MRC p15,0,Rd,cr1,cr0,0:      SCTLR -> 0x8ED187D
[CPU0] FE0A0094: MCR p15,0,Rd,cr15,cr5,0: INV_DCACHE <- 0x0       
[CPU0] FE0A0098: MCR p15, ...          : CACHEMAINT x1 (omitted)
[CPU0] FE0A009C: MCR p15,0,Rd,cr1,cr0,0:      SCTLR <- 0x48ED187D

m1k6

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Re: CHDK cpuinfo (portable code, also digic 6)
« Reply #10 on: September 03, 2016, 02:21:03 PM »
Here's the information from the 1200D:
Code: [Select]
CHDK CPU info for 0x327 1200D
-----------------------------
ID 0x41059461
 Revision 0x1 1
 Part 0x946 2374
 ARM Arch 0x5 5
 Variant 0x0 0
 Implementor 0x41 65
Cache type 0x0F112112
 Icache words/line 0x2 2 [8]
 Icache absent 0x0 0
 Icache assoc 0x2 2
 Icache size 0x4 4 [8K]
 Reserved0_2 0x0 0
 Dcache words/line 0x2 2 [8]
 Dcache absent 0x0 0
 Dcache assoc 0x2 2
 Dcache size 0x4 4 [8K]
 Reserved1_2 0x0 0
 Harvard/unified 0x1 1
 Cache type 0x7 7
 Reserved2_3 0x0 0
TCP type 0x000C00C0
 Reserved0_2 0x0 0
 ITCM absent 0x0 0
 Reserved1_3 0x0 0
 ITCM size 0x3 3 [4K]
 Reserved2_4 0x0 0
 DTCM absent 0x0 0
 Reserved3_2 0x0 0
 DTCM size 0x3 3 [4K]
 Reserved4_10 0x0 0
Control 0x0005107D
 Protect enable 0x1 1
 Reserved0_1 0x0 0
 Dcache enable 0x1 1
 Reserved1_4 0xF 15
 Big endian 0x0 0
 Reserved2_4 0x0 0
 Icache enable 0x1 1
 Alt vector 0x0 0
 Cache RRR 0x0 0
 Disble load TBIT 0x0 0
 DTCM enable 0x1 1
 DTCM mode 0x0 0
 ITCM enable 0x1 1
 ITCM mode 0x0 0
 Reserved3_12 0x0 0
Protection Region 0 0x0000003F
 Enable 0x1 1
 Size 0x1F 31 [4G]
 Undef0_7 0x0 0
 Base 0x0 0 [0x00000000]
Protection Region 1 0x0000003D
 Enable 0x1 1
 Size 0x1E 30 [2G]
 Undef0_7 0x0 0
 Base 0x0 0 [0x00000000]
Protection Region 2 0xE0000039
 Enable 0x1 1
 Size 0x1C 28 [512M]
 Undef0_7 0x0 0
 Base 0x70000 458752 [0xE0000000]
Protection Region 3 0xC0000039
 Enable 0x1 1
 Size 0x1C 28 [512M]
 Undef0_7 0x0 0
 Base 0x60000 393216 [0xC0000000]
Protection Region 4 0xFF00002F
 Enable 0x1 1
 Size 0x17 23 [16M]
 Undef0_7 0x0 0
 Base 0x7F800 522240 [0xFF000000]
Protection Region 5 0x00000037
 Enable 0x1 1
 Size 0x1B 27 [256M]
 Undef0_7 0x0 0
 Base 0x0 0 [0x00000000]
Protection Region 6 0xF780002D
 Enable 0x1 1
 Size 0x16 22 [8M]
 Undef0_7 0x0 0
 Base 0x7BC00 506880 [0xF7800000]
Protection Region 7 0x00000000
 Enable 0x0 0
 Size 0x0 0 [invalid]
 Undef0_7 0x0 0
 Base 0x0 0 [0x00000000]
Region data perms 0x03333333
 Region 0 0x3 3 [P:RW U:RW]
 Region 1 0x3 3 [P:RW U:RW]
 Region 2 0x3 3 [P:RW U:RW]
 Region 3 0x3 3 [P:RW U:RW]
 Region 4 0x3 3 [P:RW U:RW]
 Region 5 0x3 3 [P:RW U:RW]
 Region 6 0x3 3 [P:RW U:RW]
 Region 7 0x0 0 [P:-- U:--]
Region inst perms 0x03333333
 Region 0 0x3 3 [P:RW U:RW]
 Region 1 0x3 3 [P:RW U:RW]
 Region 2 0x3 3 [P:RW U:RW]
 Region 3 0x3 3 [P:RW U:RW]
 Region 4 0x3 3 [P:RW U:RW]
 Region 5 0x3 3 [P:RW U:RW]
 Region 6 0x3 3 [P:RW U:RW]
 Region 7 0x0 0 [P:-- U:--]
DCache cfg 0x00000070
 Region 0 0x0 0
 Region 1 0x0 0
 Region 2 0x0 0
 Region 3 0x0 0
 Region 4 0x1 1
 Region 5 0x1 1
 Region 6 0x1 1
 Region 7 0x0 0
ICache cfg 0x00000070
 Region 0 0x0 0
 Region 1 0x0 0
 Region 2 0x0 0
 Region 3 0x0 0
 Region 4 0x1 1
 Region 5 0x1 1
 Region 6 0x1 1
 Region 7 0x0 0
Write buffer 0x00000070
 Region 0 0x0 0
 Region 1 0x0 0
 Region 2 0x0 0
 Region 3 0x0 0
 Region 4 0x1 1
 Region 5 0x1 1
 Region 6 0x1 1
 Region 7 0x0 0
DTCM cfg 0x400000006
 Reserved0_1 0x0 0
 Size 0x3 3 [4K]
 Undef0_7 0x0 0
 Base 0x20000 131072 [0x40000000]
ITCM cfg 0x00000006
 Reserved0_1 0x0 0
 Size 0x3 3 [4K]
 Undef0_7 0x0 0
 Base 0x0 0 [0x00000000]


g3gg0

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Re: CHDK cpuinfo (portable code, also digic 6)
« Reply #11 on: November 12, 2016, 04:47:03 PM »
about cache hack:
any idea how the cache gets accessible via AXI if AXISCEN in "c1, Auxiliary Control Register" is enabled?

9-24 in R4 TRM talks about AXI accesses to cache, after the bit is enabled.
but talks only about hardware lines ARUSERS and ARADDRS...

so i guess the CPU must use its AXI master interface to access its own AXI slave which routes access to caches.
the AxUSERM's bit 3 must be set for this access. somehow. probably MPU region attributes...?
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g3gg0

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Re: CHDK cpuinfo (portable code, also digic 6)
« Reply #12 on: November 12, 2016, 05:10:27 PM »
but then still we cannot lock down the cache :(
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Ant123

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Re: CHDK cpuinfo (portable code, also digic 6)
« Reply #13 on: November 12, 2016, 07:52:48 PM »
Maybe dubug unit  in Monitor debug-mode can be used instead cache hacks?

g3gg0

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Re: CHDK cpuinfo (portable code, also digic 6)
« Reply #14 on: November 12, 2016, 08:03:32 PM »
well, it can be more like a cache-hack-less gdbstub with a hand full (8 i guess) breakpoints available...

this hardware module might help us to intercept instructions, just like the gdbstub i coded once.
instead of patching a trapping instruction, this hardware module (using monitor mode) could probably make us handle hijacks etc.

but patching flash data (like some patches already do) will still not be possible with a low overhead.
(yeah we could break on memory access and handle the replacement in the monitor handler, but that takes time)
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Ant123

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Re: CHDK cpuinfo (portable code, also digic 6)
« Reply #15 on: November 12, 2016, 08:40:17 PM »
But I have truble with access to memory-mapped debug registers. Maybe MPU need to be programmed for it?

g3gg0

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Re: CHDK cpuinfo (portable code, also digic 6)
« Reply #16 on: November 12, 2016, 08:59:16 PM »
most probably, yes. iirc that area wasnt accessible by default.
0xA0000000 seams reasonable as there is nothing mapped there.
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Ant123

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Re: CHDK cpuinfo (portable code, also digic 6)
« Reply #17 on: November 13, 2016, 02:48:50 PM »
Programming MPU does not help:
Code: [Select]
MPU region 7 access control 0x00000324
  Region attributes    0x24 36 [Inner Non-cacheable; Outer Non-cacheable; Shared]
  -                    0x0 0
  Access permission    0x3 3 [P:RW U:RW]
  -                    0x0 0
  Execute never        0x0 0
Debug ID Register 0x77040013
  (raw value)          0x77040013 1996750867
Debug ROM Address Register 0xA0000003
  (raw value)          0xA0000003 -1610612733
Debug Self Address Offset Register 0x00007003
  (raw value)          0x7003 28675
Debug Status and Control Register 0x02000002
  (raw value)          0x2000002 33554434
Debug ID Register MAPPED 0xAAAEA6AA
  (raw value)          0xAAAEA6AA -1431394646

Reading memory-mapped debug registers gives a lot of garbage:
Code: [Select]
0xa0007000: 0xaaaea6aa 0xaaaaaaa9 0xabaaaaaa 0xaaaba62a
0xa0007010: 0xaaa2eaaa 0xeaaaaa2a 0xa8aaaaaa 0xaaaaaaaa
0xa0007020: 0xabeaaaa9 0xaaaaea8a 0xaaaaeaab 0xaa8aaaaa
0xa0007030: 0xaaaa2aaa 0xaaa8aaaa 0xbaaaaaba 0xaaaaaaaa
0xa0007040: 0xaaaaaaaa 0xaaaaabaa 0xaaaaaeaa 0x2aaaaaab
0xa0007050: 0xeaaeaaba 0xaaaaaaea 0xaaaaaaba 0xaabaaaab
0xa0007060: 0xeaaaaaaa 0xaeaaaaaa 0xaaaaaaae 0xaaaaaaaf
0xa0007070: 0xaaaaaaaa 0xaaa2aaa2 0xaaaaaaaa 0xa2aaaaae
0xa0007080: 0xaea082aa 0xaaaaaaaa 0xabaeaaaa 0xaaaaaaaa
0xa0007090: 0xaaeaaaaa 0xaaaaaaaa 0xbaaaeaaa 0xaaaaeaaa
0xa00070a0: 0xabfeabaa 0xabaaeb2e 0xaeaaaaaa 0xaaeeaaaa
0xa00070b0: 0xaaaaaaaa 0xa8aaaaaa 0xa8faaaaa 0xaaaaeaaa
0xa00070c0: 0xeaaaaaaa 0xaaaaaaaa 0xeaaaaa8a 0xaaaaaaab
0xa00070d0: 0xaaaaaaaa 0xaaaa8aaa 0xaaaaaaae 0x8eaaaaaa
0xa00070e0: 0xaaaaaaaa 0xaa2a2aaa 0xaeaaaaea 0xbaaaaaaa
0xa00070f0: 0xaababaaa 0xaaaa2aaa 0xaaaaa2a8 0xaaa2aaaa

g3gg0

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Re: CHDK cpuinfo (portable code, also digic 6)
« Reply #18 on: November 13, 2016, 09:03:47 PM »
boo, unexpected :(
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Ant123

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Re: CHDK cpuinfo (portable code, also digic 6)
« Reply #19 on: November 13, 2016, 09:31:05 PM »
And I'm reading the same values at addresses 0x00007000, 0x20007000, 0x40007000, 0x80007000, 0xA0007000.
There is something wrong with memory access, but I don't know where...

g3gg0

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Re: CHDK cpuinfo (portable code, also digic 6)
« Reply #20 on: November 13, 2016, 10:18:53 PM »
yeah that pattern reminds me of the data you read when there is no memory at this address.
it just returns random data, where many bits are stuck and some may toggle at random.
(e.g. when reading the second flash chip if there is none)
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twentephotography

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is there alredy ML for 1300d pleas help me ??
« Reply #21 on: December 16, 2016, 12:33:20 PM »
There is already ML for 1300d
I have tried giving the file error

I do not know what I am doing wrong ???

businessclass

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Re: CHDK cpuinfo (portable code, also digic 6)
« Reply #22 on: March 23, 2017, 05:54:02 AM »
Here's the output for 760D. it looks identical to that of 7D2 except for the CPU info ID 0x347

Code: [Select]
CHDK CPU info for 0x347 unknown
-------------------------------
ID                    0x411FC143
  Revision                         0x3    3
  Part                             0xC14  3092
  ARM Arch                         0xF    15
  Variant                          0x1    1
  Implementor                      0x41   65
Cache type            0x8003C003
  Icache min words/line            0x3   3 [8]
  (zero)                           0x0 0
  L1 Icache policy                 0x3 3
  Dcache min  words/line           0x3 3 [8]
  Exclusive Reservation Granule    0x0 0 [no info]
  Cache Writeback Granule          0x0 0 [no info]
  (zero)                           0x0 0
  (register format)                0x4 4
TCM type              0x00010001
  (raw value)                      0x10001 65537
MPU type                           0x00000800
  S                                0x0 0
  -                                0x0 0
  Num MPU regions                  0x8 8
Processor feature 0   0x00000131
  ARM inst set                     0x1 1
  Thumb inst set                   0x3 3
  Jazelle inst set                 0x1 1
  ThumbEE inst set                 0x0 0
  -                                0x0 0
Processor feature 1   0x00000001
  Programmers' model               0x1 1
  Security extensions              0x0 0
  Microcontr. prog model           0x0 0
  -                                0x0 0
Debug feature         0x00010400
  (raw value)                      0x10400 66560
Aux feature           0x00000000
  (raw value)                      0x0 0
Mem model feature 0   0x00210030
  VMSA support                     0x0 0
  PMSA support                     0x3 3
  Cache coherence                  0x0 0
  Outer sharable                   0x0 0
  TCM support                      0x1 1
  Auxilliary registers             0x2 2
  FCSE support                     0x0 0
  -                                0x0 0
Mem model feature 1   0x00000000
  L1 Harvard cache VA              0x0 0
  L1 unified cache VA              0x0 0
  L1 Harvard cache s/w             0x0 0
  L1 unified cache s/w             0x0 0
  L1 Harvard cache                 0x0 0
  L1 unified cache                 0x0 0
  L1 cache test & clean            0x0 0
  Branch predictor                 0x0 0
Mem model feature 2   0x01200000
  L1 Harvard fg prefetch           0x0 0
  L1 Harvard bg prefetch           0x0 0
  L1 Harvard range                 0x0 0
  Harvard TLB                      0x0 0
  Unified TLB                      0x0 0
  Mem barrier                      0x2 2
  WFI stall                        0x1 1
  HW access flag                   0x0 0
Mem model feature 3   0x00000011
  Cache maintain MVA               0x1 1
  Cache maintain s/w               0x1 1
  BP maintain                      0x0 0
  -                                0x0 0
  Supersection support             0x0 0
ISA feature 0         0x01101111
  Swap instrs                      0x1 1
  Bitcount instrs                  0x1 1
  Bitfield instrs                  0x1 1
  CmpBranch instrs                 0x1 1
  Coproc instrs                    0x0 0
  Debug instrs                     0x1 1
  Divide instrs                    0x1 1
  -                                0x0 0
ISA feature 1         0x13112111
  Endian instrs                    0x1 1
  Exception instrs                 0x1 1
  Exception AR instrs              0x1 1
  Extend instrs                    0x2 2
  IfThen instrs                    0x1 1
  Immediate instrs                 0x1 1
  Interwork instrs                 0x3 3
  Jazelle instrs                   0x1 1
ISA feature 2         0x21232131
  LoadStore instrs                 0x1 1
  Memhint instrs                   0x3 3
  MultipleAccess Interruptible instructions 0x1 1
  Mult instrs                      0x2 2
  MultS instrs                     0x3 3
  MultU instrs                     0x2 2
  PSR AR instrs                    0x1 1
  Reversal instrs                  0x2 2
ISA feature 3         0x01112131
  Saturate instrs                  0x1 1
  SIMD instrs                      0x3 3
  SVC instrs                       0x1 1
  SynchPrim instrs                 0x2 2
  TabBranch instrs                 0x1 1
  ThumbCopy instrs                 0x1 1
  TrueNOP instrs                   0x1 1
  T2 Exec Env instrs               0x0 0
ISA feature 4         0x00010142
  Unprivileged instrs              0x2 2
  WithShifts instrs                0x4 4
  Writeback instrs                 0x1 1
  SMC instrs                       0x0 0
  Barrier instrs                   0x1 1
  SynchPrim_instrs_frac            0x0 0
  PSR_M instrs                     0x0 0
  -                                0x0 0
ISA feature 5         0x00000000
  -                                0x0 0
Cache level ID        0x09000003
  Cache type, level 1              0x3 3 [Separate Icache, Dcache]
  Cache type, level 2              0x0 0 [no cache]
  Cache type, level 3              0x0 0 [no cache]
  Cache type, level 4              0x0 0 [no cache]
  Cache type, level 5              0x0 0 [no cache]
  Cache type, level 6              0x0 0 [no cache]
  Cache type, level 7              0x0 0 [no cache]
  Cache type, level 8              0x0 0 [no cache]
  Level of coherency               0x1 1
  Level of unification             0x1 1
  (zero)                           0x0 0
Cache size ID reg (data, level10) 0xF00FE019
  Line size in words               0x1 1 [8]
  Associativity                    0x3 3 [4]
  Number of sets                   0x7F 127 [128]
  Write allocation                 0x1 1
  Read allocation                  0x1 1
  Write back                       0x1 1
  Write through                    0x1 1
Cache size ID reg (inst, level10) 0xF00FE019
  Line size in words               0x1 1 [8]
  Associativity                    0x3 3 [4]
  Number of sets                   0xF7 127 [128]
  Write association                0x1 1
  Read association                 0x1 1
  Write back                       0x1 1
  Write through                    0x1 1
Build options 1       0x00010000
  (raw value)                      0x10000 65536
Build options 2       0x00CFC010
  (raw value)                      0xCFC010 13615120
ATCM region reg       0x00000015
  Enabled                          0x1 1
  -                                0x0 0
  Size                             0x5 5 [16K]
  -                                0x0 0
  Base address                     0x0 0 [0x00000000]
BTCM region reg       0x8000001D
  Enabled                          0x1 1
  -                                0x0 0
  Size                             0x7 7 [64K]
  -                                0x0 0
  Base address                     0x80000 524288 [0x80000000]
MPU region 0 base     0x00000000
  Base address                     0x0 0
MPU region 0 size & enable 0x0000003F
  Enabled                          0x1 1
  Size                             0x1F 31 [4G]
  -                                0x0 0
  Sub-region disabled              0x0 0 [0x00000000]
MPU region 0 access control 0x00000320
  Region attributes                0x20 32 [Inner Non-cachable; Outer Non-cachable; Non-shared]
  -                                0x0 0
  Access permissions               0x3 3 [P:RW U:RW]
  -                                0x0 0
  Execute never                    0x0 0
MPU region 1 base     0x00000000
  Base address                     0x0 0
MPU region 1 size & enable 0x0000003B
  Enabled                          0x1 1
  Size                             0x1D 29 [1G]
  -                                0x0 0
  Sub-region disabled              0x0 0 [00000000]
MPU region 1 access control 0x00000329
  Region attributes                0x29 41 [Inner Write-back, write-allocate; Outer Write-back, write-allocate; Non-shared]
  -                                0x0 0
  Access permissions               0x3 3 [P:RW U:RW]
  -                                0x0 0
  Execute never                    0x0 0
MPU region 2 base     0xBFE00000
  Base address                     0xBFE00000 -1075838976
MPU region 2 size & enable 0x00000029
  Enabled                          0x1 1
  Size                             0x14 20 [2M]
  -                                0x0 0
  Sub-regions disabled             0x0 0 [00000000]
MPU region 2 access control 0x000000324
  Region attributes                0x24 36 [Inner Non-cachable; Outer non-cachable; Shared]
  -                                0x0 0
  Access permissions               0x3 3 [P:RW U:RW]
  -                                0x0 0
  Execute never                    0x0 0
MPU revision 3 base   0xC0000000
  Base address                     0xC0000000 - -1073741824
MPU region 3 size & enable         0x0000003B
  Enabled                          0x1 1
  Size                             0x1D 29 [1G]
  -                                0x0 0
  Sub-regions disabled             0x0 0 [00000000]
MPU region 3 access control 0x00000305
  Region attributes                0x5 5 [Sharable device; Sharable]
  -                                0x0 0
  Access permissions               0x3 3 [P:RW U:RW]
  -                                0x0 0
  Execute never                    0x0 0
MPU region 4 base     0xDFE00000
  Base address                     0xDFE00000 -538968064
MPU region 4 size & enable 0x00000029
  Enabled                          0x1 1
  Size                             0x14 20 [2M]
  -                                0x0 0
  Sub-regions disabled             0x0 0 [00000000]
MPU region 4 access control 0x00000324
  Region attributes                0x24 36 [Inner Non-cachable; Outer Non-cachable; Shared]
  -                                0x0 0
  Access permissions               0x3 3 [P:RW U:RW]
  -                                0x0 0
  Execute never                    0x0 0
MPU region 5 base     0xEE000000
  Base address                     0xEE000000 3019898888
MPU region 5 size & enable 0x00000031
  Enabled                          0x1 1
  Size                             0x18 24 [32M]
  -                                0x0 0
  Sub-regions disabled             0x0 0 [00000000]
MPU region 5 access control 0x00000329
  Region attributes                0x29 [Inner Write-back, write-allocate; Outer Write-back, write-allocate; Non-shared]
  -                                0x0 0
  Access permissions               0x3 3 [P:RW U:RW]
  -                                0x0 0
  Execute never                    0x0 0
MPU region 6 base    0xFE000000
  Base address                     0xFE000000 -33554433
MPU region 6 size & enable 0x00000031
  Region attributes                0x29 41 [Inner Write-back, write-allocate; Outer Write-back, write-allocate; Non-shared]
  -                                0x0 0
  Access permission                0x3 3 [P:RW U:RW]
  -                                0x0 0
  Execute never                    0x0 0
MPU region 7 base    0x00000000
  Base address                     0x0 0
MPU region 7 size & enable 0x000000000
  Enabled                          0x0 0
  Size                             0x0 0 [invalid]
  -                                0x0 0
  Sub-regions disabled             0x0 0 [00000000]
MPU region 7 access control 0x00000000
  Region attributes                0x0 0 [Strongly ordered, sharable; ]
  -                                0x0 0
  Access permissions               0x0 0 [P:-- U:--]
  -                                0x0 0
  Execute never                    0x0 0

vapdesignstudios

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Re: CHDK cpuinfo (portable code, also digic 6)
« Reply #23 on: May 26, 2017, 02:13:06 PM »
Hi do i have to replace only the cpu  CPUI1300.FIR to get ML ? only that's it & format card before ?
thanks a lot

Walter Schulz

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Re: CHDK cpuinfo (portable code, also digic 6)
« Reply #24 on: May 28, 2017, 07:07:12 PM »
No.

emklap

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Re: CHDK cpuinfo (portable code, also digic 6)
« Reply #25 on: May 30, 2017, 06:47:24 PM »
hey ALEX,on the 80d i got the same information  as atonal got on the 7d2.only difference was the first line which read -
CHDK CPU info for 0x350 80d
-----------------------------
ID              0x411FC143.If you need picture proof just tell me.

80D Fw1.02 I have similar data but a few lines more on page1, and page 4

Extra on page 1
Multiprocessor ID  0x00000000
  (raw value)           0x0 0

Extra on page 4
SCTRL        0x08E5187D
  (raw value)           0x08E5187D 149231741
ACTRL        0x00000030
  (raw value)           0x20 32
ACTRL2        0x00000000
  (raw value)           0x0 0
CPACR        0x00000000
  (raw value)           0x0 0

Page 1





Page 4






300D,40D,80D, 18-55IS EFS, Tokina17-55/F2.8, ,70-200LIS/F4, 50EF/F1.8, extender 1.4, extender 2III, EX-430II,Sigma 8-16

g3gg0

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Re: CHDK cpuinfo (portable code, also digic 6)
« Reply #26 on: September 02, 2017, 11:19:28 PM »
...and here from the 5Ds, inverted C64 style


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Walter Schulz

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Re: CHDK cpuinfo (portable code, also digic 6)
« Reply #27 on: September 03, 2017, 04:34:08 PM »
5DS, who would have guessed this
cam being the first D6 cam with bootflag set? Dual D6 ...
Congrats!

Um ... this is not QEMU, right?

g3gg0

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Re: CHDK cpuinfo (portable code, also digic 6)
« Reply #28 on: September 03, 2017, 10:55:53 PM »
yeah its a physical 5Ds with bootflag enabled now :)
basically did a1ex prepare everything needed to do that.

now comes the really hard part - porting!
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nikfreak

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Re: CHDK cpuinfo (portable code, also digic 6)
« Reply #29 on: September 04, 2017, 12:02:11 AM »
5Ds + g3gg0  :-*
crossing the fingers. Congrats.
70D.112 & 100D.101

samuel.cabral

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Re: CHDK cpuinfo (portable code, also digic 6)
« Reply #30 on: September 04, 2017, 08:41:52 PM »
yeah its a physical 5Ds with bootflag enabled now :)
basically did a1ex prepare everything needed to do that.

now comes the really hard part - porting!

Maybe it's too soon but... Can we expect ports to Eos M5, M6, M100?

g3gg0

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Re: CHDK cpuinfo (portable code, also digic 6)
« Reply #31 on: September 05, 2017, 08:00:47 PM »
graphical flash dumper in beta test phase.
you may also call it "3456 parallel led dumper" ;)
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g3gg0

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Re: CHDK cpuinfo (portable code, also digic 6)
« Reply #32 on: September 05, 2017, 08:03:00 PM »
Maybe it's too soon

not just "maybe" - its definitely too soon.
i got hands on a 5Ds and will play now a bit.
this does not imply that there will be a port.
especially as its just given as a loan.

it just means that we can play now a bit
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Walter Schulz

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Re: CHDK cpuinfo (portable code, also digic 6)
« Reply #33 on: September 05, 2017, 08:08:42 PM »
Maybe it's too soon but... Can we expect ports to Eos M5, M6, M100?

Nope. M5, M100 are running PowerShot code. Devs once mentioned it is more likely to port ML to Nikon ...
Use CHDK instead.
Don't know about M6.

a1ex

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Re: CHDK cpuinfo (portable code, also digic 6)
« Reply #34 on: September 05, 2017, 08:18:36 PM »
M6 too - https://chdk.setepontos.com/index.php?topic=13210.0

M100? When did that appear? (I thought it's a typo for M10...)

samuel.cabral

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Re: CHDK cpuinfo (portable code, also digic 6)
« Reply #35 on: September 05, 2017, 10:13:53 PM »
M6 too - https://chdk.setepontos.com/index.php?topic=13210.0

M100? When did that appear? (I thought it's a typo for M10...)

lol... It's quite new! But it's cheaper (and "weaker") than the m5 and m6!
Hope that we can have raw video in these low budget new cameras.

Walter Schulz

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Re: CHDK cpuinfo (portable code, also digic 6)
« Reply #36 on: September 06, 2017, 07:37:35 AM »