i wont explain 4-way set associative caches in detail.
there are enough online guides available.
e.g.
http://www.ecs.umass.edu/ece/koren/architecture/Cache/tutorial.htmlin short:
when the cpu reads DATA or INSTRUCTION first the cache is asked.
the ADDRESS that should get read from memory is split in 2 parts:
ADDRESS = (TAG | OFFSET)
cache has two RAMs that are not visible normally.
one is called TAG-RAM, the other DATA-RAM.
now the cache looks in TAG-RAM if the address is cached and returns the data if there was a hit.
if(TAGRAM[GET_OFFSET(address)] == GET_TAG(address))
{
return DATARAM[GET_OFFSET(address)];
}
if there was no hit, the data is placed in cache like this:
DATARAM[GET_OFFSET(address)] = data_from_ram;
TAGRAM[GET_OFFSET(address)] = GET_TAG(address);
that happens all the time when something is read from ram/flash.
when patching cache content via MCR/MRC we manually set the OFFSET and then can read/write TAG and DATA.
this way we are telling the cache: "hey you already have somewhen read the data the CPU just wanted to read. just read it from you DATA_RAM"
now the cache supports another feature - locking.
when locking one of the four caches, the cache logics wont overwrite its content anymore.
the patch is "permanent" until RESET or someone invalidates the cache contents.
