Running tasks on CPU1 (second CPU)

Started by names_are_hard, June 18, 2021, 05:33:01 PM

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names_are_hard

Some cams are dual-core.  I've worked out how to start tasks on the second core.  Cores can communicate using at least semaphores, so we can do cooperative multi-tasking.  This should be quite useful for splitting work, especially anything that can be easily pipelined or batched.  E.g., expensive operations on a sequence of frames or images - these can alternate between cores or be picked up from a queue by whichever core becomes ready first.  For CPU bound tasks this may be a large improvement.

I seem to recall CHDK / srsa already knew this, from some other thread, but I couldn't find it and there were no details.

On 200D, 1.0.1, df008f0a is task_create_ex(), which is like task_create() but with an extra arg that selects CPU to use.  I've tested 0 and 1, I believe -1 means "run on either/all CPU(s)", but this is untested. 

Small code example:


static struct semaphore *mp_sem; // for multi-process cooperation

static void cpu0_test()
{
    while(1)
    {
        DryosDebugMsg(0, 15, "Hello from CPU0");
        take_semaphore(mp_sem, 0);
        msleep(1000);
        give_semaphore(mp_sem);
    }
}

static void cpu1_test()
{
    while(1)
    {
        DryosDebugMsg(0, 15, "Hello from CPU1");
        take_semaphore(mp_sem, 0);
        msleep(1000);
        give_semaphore(mp_sem);
    }
}

static void run_test()
{
    mp_sem = create_named_semaphore("mp_sem", 1);
    task_create_ex("cpu1_test", 0x1e, 0, cpu1_test, 0, 1);
    task_create_ex("cpu0_test", 0x1e, 0, cpu0_test, 0, 0);
    return;
}


This leads to the CPUs taking turns to print, once per second.

ilia3101

Nice! Is this only for new cams?

What about DIGIC 5 and (like 5D mark 3 or 7D)

Seriously this is potentially amazing.

Danne

5D mark III, single core?
Anyway. Great work @names_are_hard.

names_are_hard

I've only confirmed this on 200D.  I'd expect all Digic 7 and 8 to be similar.  Maybe the dual processor Digic 4, 5 and 6 will use a similar API?  Maybe not.

reyalp

Quote from: names_are_hard on June 18, 2021, 05:33:01 PM
I seem to recall CHDK / srsa already knew this, from some other thread, but I couldn't find it and there were no details.
There was some discussion in https://chdk.setepontos.com/index.php?topic=13773.10

Quote
I've only confirmed this on 200D.  I'd expect all Digic 7 and 8 to be similar.  Maybe the dual processor Digic 4, 5 and 6 will use a similar API?  Maybe not.
AFAIK the earlier "dual digic" ran a separate firmware on each CPU, see https://magiclantern.fandom.com/wiki/7D_internals and https://web.archive.org/web/20130309115612/http://www.magiclantern.fm/whats-new/104-releases/140-first-7d-alpha-released

Single Digic 6 (on P&S at least) has a somewhat similar situation: "Omar" is another Cortex R4, similar but not identical to the main core, which runs its own stripped down instance of DryOS. It's not too hard to run code there, but obviously synchronization would be more complicated https://chdk.setepontos.com/index.php?topic=11316.msg119473#msg119473

kitor

QuoteSingle Digic 6 (on P&S at least) has a somewhat similar situation: "Omar" is another Cortex R4, similar but not identical to the main core, which runs its own stripped down instance of DryOS.

This is also true for D7 and D8. Just secondary cores seems to be Xtensa (at least those we explored already - Zico, Lime).

Main firmware runs on Dual core ARM, this is where this thread applies.
Too many Canon cameras.
If you have a dead R, RP, 250D mainboard (e.g. after camera repair) and want to donate for experiments, I'll cover shipping costs.