Author Topic: 5D2 - QEMU & DM Log files for R&D  (Read 1274 times)

reddeercity

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5D2 - QEMU & DM Log files for R&D
« on: December 16, 2017, 11:55:52 PM »
Starting a new thread for the 5d2 dm-log and other log files for r&d , didn't what to clutter up the 12-bit (and 10-bit) RAW video development discussion thread
so I saw some interesting things in dm-0001.log file from my bitbucket downloads
Code: [Select]
1A2C2>    PropMgr:ff99bbdc:01:03: MovieParamData
1A31B>    PropMgr:ff99b5b4:01:03: #mode 0 size 0x0 , framerate 0x18 , type 0xc
Code: [Select]
       
6AC67>    Startup:ff8e5f88:98:03: GetImageTrimming X(2976)=0(2414, 2416), Y(1928)=0(1552, 1548)

Code: [Select]
3003C>    Startup:ff814378:8b:03: startupPrepareCapture
304F4>    Startup:ff8b89c4:80:03: MemMgr 0 2
30539>    Startup:ff8b89c4:80:03: MemMgr 0 0
3055C>    Startup:ff8b89c4:80:03: MemMgr 0 4
3057D>    Startup:ff8b89c4:80:03: MemMgr 0 0
306C5>    Startup:ff8b5ea4:80:03: RearrangeMemMgr 0 5
30712>    Startup:ff8b2d54:80:01: ###### AllocateMemoryFromShootMemoryObject 1
3073B>    Startup:ff8b2dfc:80:01: ###### 0 0x73CFE0 0x73CFE0
3076B>    Startup:ff8b2dfc:80:01: ###### 1 0x73CFE8 0x73CF2C
30797>    Startup:ff8b2e28:80:01: ###### 1 pMemoryUnit 0x73CF2C 0x73D3B0
307D2>    Startup:ff8b2e58:80:01: AllocatableSizeOfPackHeap 30408592, 16384, 16384
30809>    Startup:ff8b30e0:80:01: !!AllocateMemory 16384
30891>    Startup:ff8b2f28:80:01: AllocateMemoryFromShootMemoryObject 1 97517232 16384 0x0073d518
308D8>    Startup:ff8b2f44:80:01: ###### VirtualXXXFreeSize1 97517232 137296720
30920>    Startup:ff8b32d0:80:01: ###### VirtualXXXFreeSize2 97500836 137296720
30959>    Startup:ff8b32e4:80:01: ###### !! AllocateMemoryFromShootMemoryObject hMemSuite 0x73D518
30983>    Startup:ff8b5d40:80:05: Enter AllocateMEM3 0x4000 JOB

Bet you seen this before  ;D
Code: [Select]
3B836>     RscMgr:ff8af44c:80:03: SetBusy 0x50(0x50)(0x10)
Shoot Capture
Code: [Select]
4189C> ShootCaptu:ff881d04:93:03: scsProperty ID=0x0(0x0)
41988> ShootCaptu:ff87f820:93:03: scsInit
41A4B> ShootCaptu:00095f98:00:00: *** register_interrupt(0x0, 0x33, 0xff871c50, 0x0), from ff871db8
41CB9> ShootCaptu:00095f98:00:00: *** register_interrupt("CAPREADY", 0x51, 0xffa35980, 0x0), from ffa359f4
42060> ShootCaptu:ff9a77d0:00:01: [CLKSAVER] ��ClockSave Out��
423A9> ShootCaptu:00095f98:00:00: *** register_interrupt("JpCoreIntrHandler", 0x64, 0xff9a5954, 0x0), from ff9a5c80
42849> **INT-64h*:00095c38:00:00: >>> INT-64h JpCoreIntrHandler ff9a5954(0)
428A0> **INT-64h*:0000057c:00:00: <<< INT-64h done
42EEC> ShootCaptu:00095f98:00:00: *** register_interrupt("JpCore2IntrHandler", 0xa3, 0xff9a64bc, 0x0), from ff9a6774
42F82> ShootCaptu:00095f98:00:00: *** register_interrupt("CompleteReadOperation", 0x60, 0xffb273d8, 0x0), from ffb27454
4303D> ShootCaptu:00095f98:00:00: *** register_interrupt("AfComplete", 0x61, 0xff9a8c00, 0x0), from ff9a8df8
43092> ShootCaptu:00095f98:00:00: *** register_interrupt("AfOverRun", 0x62, 0xff9a8d84, 0x0), from ffb26df8
430E6> ShootCaptu:00095f98:00:00: *** register_interrupt("ADKIZ", 0x65, 0xffb27fac, 0x0), from ffb26dfc
43161> ShootCaptu:00095f98:00:00: *** register_interrupt("Obinteg", 0x63, 0xffb27744, 0x0), from ffb26e04
431B1> ShootCaptu:00095f98:00:00: *** register_interrupt("WbInteg", 0x66, 0xffb26754, 0x0), from ffb267d4
431FC> ShootCaptu:00095f98:00:00: *** register_interrupt("WbBlock", 0x67, 0xffb2677c, 0x0), from ffb26e08
4325E> ShootCaptu:00095f98:00:00: *** register_interrupt("WEDmac0Interrupt", 0x58, 0xff9a4038 "[ENG] WriteDMACInterrupt(%d)(%#lx)(%d)", 0x0), from ff9a4438
432B3> ShootCaptu:00095f98:00:00: *** register_interrupt("WEDmac1Interrupt", 0x59, 0xff9a4038 "[ENG] WriteDMACInterrupt(%d)(%#lx)(%d)", 0x1), from ff9a4438
43307> ShootCaptu:00095f98:00:00: *** register_interrupt("WEDmac2Interrupt", 0x5a, 0xff9a4038 "[ENG] WriteDMACInterrupt(%d)(%#lx)(%d)", 0x2), from ff9a4438
4335C> ShootCaptu:00095f98:00:00: *** register_interrupt("WEDmac3Interrupt", 0x5b, 0xff9a4038 "[ENG] WriteDMACInterrupt(%d)(%#lx)(%d)", 0x3), from ff9a4438
433B2> ShootCaptu:00095f98:00:00: *** register_interrupt("WEDmac4Interrupt", 0x5c, 0xff9a4038 "[ENG] WriteDMACInterrupt(%d)(%#lx)(%d)", 0x4), from ff9a4438
43406> ShootCaptu:00095f98:00:00: *** register_interrupt("WEDmac5Interrupt", 0x6d, 0xff9a4038 "[ENG] WriteDMACInterrupt(%d)(%#lx)(%d)", 0x5), from ff9a4438
4345C> ShootCaptu:00095f98:00:00: *** register_interrupt("WEDmac6Interrupt", 0xc0, 0xff9a4038 "[ENG] WriteDMACInterrupt(%d)(%#lx)(%d)", 0x6), from ff9a4438
434B5> ShootCaptu:00095f98:00:00: *** register_interrupt("REDmac0Interrupt", 0x5d, 0xff9a426c "[ENG] ReadDMACInterrupt(%d)(%#lx)(%d)", 0x8), from ff9a4438
43509> ShootCaptu:00095f98:00:00: *** register_interrupt("REDmac1Interrupt", 0x5e, 0xff9a426c "[ENG] ReadDMACInterrupt(%d)(%#lx)(%d)", 0x9), from ff9a4438
4355E> ShootCaptu:00095f98:00:00: *** register_interrupt("REDmac2Interrupt", 0x5f, 0xff9a426c "[ENG] ReadDMACInterrupt(%d)(%#lx)(%d)", 0xa), from ff9a4438
435B2> ShootCaptu:00095f98:00:00: *** register_interrupt("REDmac3Interrupt", 0x6e, 0xff9a426c "[ENG] ReadDMACInterrupt(%d)(%#lx)(%d)", 0xb), from ff9a4438
43607> ShootCaptu:00095f98:00:00: *** register_interrupt("REDmac4Interrupt", 0xc1, 0xff9a426c "[ENG] ReadDMACInterrupt(%d)(%#lx)(%d)", 0xc), from ff9a4438
4365C> ShootCaptu:00095f98:00:00: *** register_interrupt("REDmac5Interrupt", 0xc8, 0xff9a426c "[ENG] ReadDMACInterrupt(%d)(%#lx)(%d)", 0xd), from ff9a4438
436B1> ShootCaptu:00095f98:00:00: *** register_interrupt("WEDmac7Interrupt", 0xf9, 0xff9a4038 "[ENG] WriteDMACInterrupt(%d)(%#lx)(%d)", 0x10), from ff9a4438
43708> ShootCaptu:00095f98:00:00: *** register_interrupt("WEDmac8Interrupt", 0x83, 0xff9a4038 "[ENG] WriteDMACInterrupt(%d)(%#lx)(%d)", 0x11), from ff9a4438
4375F> ShootCaptu:00095f98:00:00: *** register_interrupt("WEDmac9Interrupt", 0x8a, 0xff9a4038 "[ENG] WriteDMACInterrupt(%d)(%#lx)(%d)", 0x12), from ff9a4438
437B6> ShootCaptu:00095f98:00:00: *** register_interrupt("REDmac6Interrupt", 0x8b, 0xff9a426c "[ENG] ReadDMACInterrupt(%d)(%#lx)(%d)", 0x18), from ff9a4438
4380C> ShootCaptu:00095f98:00:00: *** register_interrupt("REDmac7Interrupt", 0x92, 0xff9a426c "[ENG] ReadDMACInterrupt(%d)(%#lx)(%d)", 0x19), from ff9a4438
4382C> **INT-0Ah*:00095c38:00:00: >>> INT-Ah Timer ff81027c(0)
4386D> **INT-0Ah*:0000057c:00:00: <<< INT-Ah done
4390D> ShootCaptu:00095f98:00:00: *** register_interrupt("CompleteOperation", 0x9a, 0xffb895c0, 0x0), from ffb26e18
43965> ShootCaptu:00095f98:00:00: *** register_interrupt("CompleteOperation", 0x93, 0xffb2a0c4, 0x0), from ffb26e1c
43EA7> ShootCaptu:ff87f908:93:03: BathtubAddress:0x5c714000, Size:65536
43F62>     RscMgr:ff8af184:80:03: ClearBusy 0x10(0x10)(0x40)

Still looking for liveview sync stuff .

reddeercity

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Re: 5D2 dm-log files for R&D
« Reply #1 on: December 17, 2017, 08:51:24 AM »
Some Liveview stuff , NTSC Sync  -- maybe ?
Code: [Select]
D7292>    Startup:ff867658:82:03: InitializeDisplayDeviceController (PUB)
D746C>    Startup:00095f98:00:00: *** register_interrupt("EngInt PBVD", 0x68, 0xff866fb4 "VdInterruptHandler img=%x bmp=%x", 0x0), from ff867688
D74D5>    Startup:00095f98:00:00: *** register_interrupt("EngInt PBVD", 0x69, 0xff86719c "!! PBERROR_InterruptHandler 0x%lX", 0x0), from ff86769c
D783D>    Startup:ff9ad254:82:02: Factory TFT Com Adjust Add  0x404c6fc4
D7886>    Startup:ff9ad268:82:02: Factory TFT Com Adjust Size 12
D78AC>    Startup:ff9ad284:82:02: Factory TFT Com Adjust R 80006 G 80540 B 81024
D7906>    Startup:ff9acee8:82:02: Factory Sync Burst Adjust Add    0x404c6f68
D7935>    Startup:ff9acefc:82:02: Factory Sync Burst Adjust Size   16
D7957>    Startup:ff9acf18:82:02: NTSC Bf   0xeb, 0xeb
D7977>    Startup:ff9acf34:82:02: NTSC Sync 0x9471, 0x94719471
D79A2>    Startup:ff9acf50:82:02: PAL  Bf   0xec, 0xec
D79C2>    Startup:ff9acf6c:82:02: PAL  Sync 0x946f, 0x946f946f
D79FE>    Startup:ff9acfb4:82:02: Factory YUV Adjust Add  0x404c6f80
D7A29>    Startup:ff9acfc8:82:02: Factory YUV Adjust Size 24
D7A49>    Startup:ff9acfe8:82:02: TFT  Y   0x80, 0x80
D7A69>    Startup:ff9ad004:82:02: TFT  UV  0x8080, 0x8080
D7A8E>    Startup:ff9ad020:82:02: NTSC Y   0x35, 0x35
D7AAE>    Startup:ff9ad03c:82:02: NTSC UV  0x2d42, 0x2d42
D7AD2>    Startup:ff9ad058:82:02: PAL  Y   0x34, 0x34
D7AF2>    Startup:ff9ad074:82:02: PAL  UV  0x3d59, 0x3d59

Lens info
Code: [Select]
F0639>    CtrlSrv:ff9caf08:83:03: CurrentLensName[EF24-70mm f/2.8L USM]
a little VSync stuff
Code: [Select]
1F6DD> GuiLockTas:ff868058:00:02: [DispCon] EnableTftIc
1F76D> GuiLockTas:00095f98:00:00: *** register_interrupt(0x0, 0x34, 0xff871c50, 0x1), from ff871db8
21AD2> **INT-0Ah*:00095c38:00:00: >>> INT-Ah Timer ff81027c(0)
21B0E> **INT-0Ah*:0000057c:00:00: <<< INT-Ah done
226AF> GuiLockTas:ff866168:82:01: WaitVSync (PRI)
226DC> GuiLockTas:ff863fb4:82:01:  RequestNotifyBlank (PRI)
22702> GuiLockTas:ff864078:82:03: RequestNotifyBlank img=0 bmp=ff864cec
23750> **INT-68h*:00095c38:00:00: >>> INT-68h EngInt PBVD ff866fb4(0)
23787> **INT-68h*:ff866ff8:82:03: VdInterruptHandler img=0 bmp=ff864cec
237B6> **INT-68h*:ff864cfc:82:01: WaitBmpCBR
237E3> **INT-68h*:0000057c:00:00: <<< INT-68h done
23809> GuiLockTas:ff8661c0:82:02: EnableTftCtrl CurrentBrightness=4
23896> GuiLockTas:00095f98:00:00: *** register_interrupt(0x0, 0x34, 0xff871c50, 0x1), from ff871db8
241E2> **INT-0Ah*:00095c38:00:00: >>> INT-Ah Timer ff81027c(0)
2421C> **INT-0Ah*:0000057c:00:00: <<< INT-Ah done
242D5> **INT-10h*:00095c38:00:00: >>> INT-10h HPTimer ff86ca8c(0)
24337> **INT-10h*:0000057c:00:00: <<< INT-10h done
268F1> **INT-0Ah*:00095c38:00:00: >>> INT-Ah Timer ff81027c(0)
26924> **INT-0Ah*:0000057c:00:00: <<< INT-Ah done
2747D> GuiLockTas:ff8658e8:82:02:   NotifyChangeTurnOnDisplay
2784C> GuiLockTas:ff864be8:82:02:  SelectParameterToBmp (PRI)
2787D> GuiLockTas:ff864a40:82:02:  SetParameterToBitmapDisplayDevice (PRI)

a1ex

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Re: 5D2 dm-log files for R&D
« Reply #2 on: December 17, 2017, 10:06:11 AM »
All of this is before Canon GUI even starts.

You'll see the same stuff (and be able to run it step by step or with additional debug infos) in QEMU, with:
Code: [Select]
./run_canon_fw.sh 5D2,firmware="boot=0" -d debugmsg ...

reddeercity

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Re: 5D2 dm-log files for R&D
« Reply #3 on: December 18, 2017, 05:27:16 AM »
Ok thanks  , I did try to run QEMU on my AMD desktop that runs the VM of Ubuntu but clashed/errors out , I'll try on my dell i5 intel laptop .
If I'm not mistaken QEMU has been update , I'll need to catch up -- last version I tried was 1.6 I think

a1ex

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Re: 5D2 dm-log files for R&D
« Reply #4 on: December 18, 2017, 04:47:06 PM »
If all else fails, check this sticky tweet and the QEMU guide. Works on Mac and Windows too.

reddeercity

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Re: 5D2 dm-log files for R&D
« Reply #5 on: December 20, 2017, 06:44:46 AM »
Ok thanks , will do  :D

reddeercity

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Re: 5D2 dm-log files for R&D
« Reply #6 on: February 04, 2018, 05:57:10 AM »
This seems the best place to continue from TFT SIO communication (tft_regs.mo) post 33  as this has to do with startup Log files  but with hdmi connected,
there seem to be a few interesting thing like hdmi audio , LCD mirroring plus getting the 2 pillow box out (5d2 only I think) if possible .
below you see canon has muted the audio for some reason , being that most if not all  hdmi chips to my knowledge support audio I can't see a reason for the mute
don't know how you would turn it on , not to sure if this would be access thought canon only firmware or something that can be enable with code from ml
Code: [Select]
6405F> GuiLockTas:ff9ade94:88:03: Pana_TurnOnHDMI (Audio = 1)
640A1> GuiLockTas:ff9ae7d0:88:05: hdmiWaitForStat (stat = 1)
640D3> GuiLockTas:ff9ae858:88:05: hdmiWaitForStat : OK (3)
6414F> GuiLockTas:ff9a77d0:00:01: [CLKSAVER] ��ClockSave In��
64188> GuiLockTas:ff9a77d0:00:01: [CLKSAVER] ��ClockSave In��
641BD> GuiLockTas:ff867374:82:16: SetPBForHDMI DispType=3 fChange=0 HDMIInit=0
64247> GuiLockTas:ff8675ec:82:02: MuteON (3220)

Something else that I saw that I wonder if it's possible to implement for digic iv , 5d2 in particular
display mirroring , back lcd & hdmi , to my knowledge I would think that both HD buffer (HDVram I think) and the VGA lcd buffer needs to enable that the same time
or some how keep the vga buffer for back lcd enable when hdmi connected
I do know that there is two different buffer from what I seem , but to turn both on ,  that would be something again a firm thing or maybe a hack
this make me believe this could be a possible , but more than likely not by me . 
Code: [Select]
731FF>    CtrlSrv:ff8251b4:00:04: < GUI Lock > GUILock_TurnOffDisplay (PUB)
732C7> GuiLockTas:ff8248bc:00:03: < GUI Lock > GUILockTask 2
7331E> GuiLockTas:ff8677ec:82:16: TurnOffDisplay (PUB) Type=3 fDisplayTurnOn=1

Maybe 3x crop mode ?
Code: [Select]
D0583> LiveViewMg:ff837594:06:01: LVCAF_StartLiveView
D060A> LiveViewMg:ff90bde8:07:03: (Called->SetAFDefaultParam)
D063F> LiveViewMg:ff90bde8:07:03:  LVAF Ver.1.1.6 for Common
D0673> LiveViewMg:ff90bde8:07:03: InHeight           = 1268
D069E> LiveViewMg:ff90bde8:07:03: InWidth            = 2040
D06C7> LiveViewMg:ff90bde8:07:03: PosY               = 518
D06EE> LiveViewMg:ff90bde8:07:03: PosX               = 910
D0718> LiveViewMg:ff90bde8:07:03: AfHeight           = 248
D073E> LiveViewMg:ff90bde8:07:03: AfWidth            = 374
D0770> LiveViewMg:ff90bde8:07:03: FE { LPF=3, HPF=2, HPF2=4, THRX2=0, H2ON=1 }
D079F> LiveViewMg:ff90bde8:07:03: TE { LPF=4, HPF=0, HPF2=4, THRX2=0, H2ON=1 }
Is liveview lcd screen yuv (rgb)4.1.1. ? could this be the reason why in 10-12bit development  we get messup liveview
Code: [Select]
D0BEC> LiveViewMg:ffa0c904:18:01: [DETFEN] DetectFace_SetDataYUV411VType LVANGEL ?  ??? interesting
Code: [Select]
D168E> LiveViewMg:ff8db56c:98:02: LVANGEL_GetAngelAndLuckyParameter 0
I can understand having 2 Vram buffer but 3 or is  one for 3x crop mode? or I'm I miss understanding
Code: [Select]
D28FA> LiveViewMg:ff8e0444:9b:03: Vram[0] = 0x41B07800
D2933> LiveViewMg:ff8e0444:9b:03: Vram[1] = 0x5C007800
D2963> LiveViewMg:ff8e0444:9b:03: Vram[2] = 0x5F607800

What the hell UHD  :)  will kind've  3840x48 almost looks like sRaw ,
Code: [Select]
D29C0> LiveViewMg:ffa0aaa0:99:02: StartRamClearPassRectangle Addr:41b07800, Width:3840, Height:48, VW:3840That's one thing I've being looking for the , the sRaw size = UHD 3840 , so if I can some how get to the regs that control sRaw I maybe get 3840 out of a processing chip .
Wishful thinking .
VGA ? of LCD , would VW 3840 have something to do with "View Width" of 3840 in a vga resolution or down scaling ?
Code: [Select]
D6E45> LiveViewMg:ffa0a924:99:02: StartRamClearPassLR Addr:5f634800 Width:600 Height:880 Gap:2640 VW:3840and again but no "ClearPassLR"
Code: [Select]
D7B53> LiveViewMg:ffa0aaa0:99:02: StartRamClearPassRectangle Addr:5f96d800, Width:3840, Height:152, VW:3840 Seem to be a resizing the full res 5616x3744 to 3:4 960x478 (back lcd screen)
could be useful in 4K/UHD/3k etc. .... for preview in realtime (theoretically)
Code: [Select]
DFB12>    CtrlSrv:ffaac1a8:83:03: DlgLiveView.c ResizeLiveViewDialog(3)
E0691>    CtrlSrv:ffb7dd28:83:03: DlgLiveView.c VisibleDialogItemForBlackout
E08C4>    CtrlSrv:ff9d999c:83:02: CalcLvVramSize VramSize X(0) Y(0) W(960) H(478)
E0EDE>    CtrlSrv:ffb781ac:83:02: SetLvMovieAspectFrameToWinSystem Aspect ImaegSize W(5616) H(3744)
E0F3D>    CtrlSrv:ff9d999c:83:02: CalcLvVramSize VramSize X(0) Y(0) W(960) H(478)
E0F76>    CtrlSrv:ffb4e3d8:83:02: GetAspectHorizontalLinePosition
E0F9F>    CtrlSrv:ffb4e3f0:83:02: uiAspectWidth(16) uiAspectHeight(9)
E0FC8>    CtrlSrv:ffb4e40c:83:02: uiImageWidth(5616) uiImageHeight(3744) uiVramHeight(478)
Crop window ? , maybe a way to expand the window area like 5d3 @ 3.5k for 5d2 of is the buffer not big enough
Code: [Select]
13C7B> LiveViewMg:ff8e6a9c:98:02: LV_GetPtpZoomWindowArea IX=2247(2416), IY=1500(1548)
13CB8> LiveViewMg:ff8e6ab8:98:02: LV_GetPtpZoomWindowArea CX=0, CY=0
Framerate I think , I have canon set to 24p
Code: [Select]
1E811> LiveViewMg:00096198:00:00: *** register_interrupt("HEAD3", 0xd9, 0xff986e2c, 0x0), from ff986ee0
1E880> LiveViewMg:00096198:00:00: *** register_interrupt("HEAD4", 0xe0, 0xff986f4c, 0x0), from ff986f98

There a lot to understand here .




reddeercity

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Re: 5D2 dm-log files for R&D
« Reply #7 on: February 06, 2018, 03:49:26 AM »
Some more fun stuff from my dm-startup log -- 
in my quest to understand everything in the startup log , I started looking in to the D4 TFT (LCD screen) In this post  here and some response from a1ex here
So let break down this part of the LOG file .   
Code: [Select]
02DB>    Startup:ff9ad254:82:02: Factory TFT Com Adjust Add  0x405c6fc4
30329>    Startup:ff9ad268:82:02: Factory TFT Com Adjust Size 12
30354>    Startup:ff9ad284:82:02: Factory TFT Com Adjust R 80006 G 80540 B 81024
303B5>    Startup:ff9acee8:82:02: Factory Sync Burst Adjust Add    0x405c6f68
303E8>    Startup:ff9acefc:82:02: Factory Sync Burst Adjust Size   16
3040D>    Startup:ff9acf18:82:02: NTSC Bf   0xeb, 0xeb
30432>    Startup:ff9acf34:82:02: NTSC Sync 0x9471, 0x94719471
30461>    Startup:ff9acf50:82:02: PAL  Bf   0xec, 0xec
30484>    Startup:ff9acf6c:82:02: PAL  Sync 0x946f, 0x946f946f
304BE>    Startup:ff9acfb4:82:02: Factory YUV Adjust Add  0x405c6f80
304ED>    Startup:ff9acfc8:82:02: Factory YUV Adjust Size 24
30511>    Startup:ff9acfe8:82:02: TFT  Y   0x80, 0x80
30554>    Startup:ff9ad004:82:02: TFT  UV  0x8080, 0x8080
30587>    Startup:ff9ad020:82:02: NTSC Y   0x35, 0x35
305AD>    Startup:ff9ad03c:82:02: NTSC UV  0x2d42, 0x2d42
305D7>    Startup:ff9ad058:82:02: PAL  Y   0x34, 0x34
305FC>    Startup:ff9ad074:82:02: PAL  UV  0x3d59, 0x3d59
306BA>    Startup:ff9a77d0:00:01: [CLKSAVER] ��ClockSave In��
306F5>    Startup:ff9a77d0:00:01: [CLKSAVER] ��ClockSave In��
3073E>    Startup:ff9a77d0:00:01: [CLKSAVER] ��ClockSave In��
307B0>    Startup:ff867780:82:03: Port Setting Fin
3082D>    Startup:ff864eec:00:03: [BmpDDev] InitializeBitmapDisplayDevice (PUB)
30B6B>    PropMgr:ff9aff0c:88:03: [EDID] PROP_CFN_TAB2 HDMI THRUE 0
30BDC>    PropMgr:ff9aff0c:88:03: [EDID] VIDEO_SYSTEM 0
30CFD>    PropMgr:ff8682d4:88:05: hdmiChangeAckCBR (0)
30D8E>       HDMI:ff868490:88:16: HPD OFF
30DC4>       HDMI:ff868214:88:05: DisconnectHDMI : Not Connected
30E00>    Startup:ff861c18:00:03: [SVG] CreateBufferMemory()
Not sure if this changes from photo mode to video mode , didn't check
Code: [Select]
30329>    Startup:ff9ad268:82:02: Factory TFT Com Adjust Size 12RGB levels
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Startup:ff9ad284:82:02: Factory TFT Com Adjust R 80006 G 80540 B 81024Maybe related to Vsync , which is a issue in 10-12bit
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303B5>    Startup:ff9acee8:82:02: Factory Sync Burst Adjust Add    0x405c6f68
303E8>    Startup:ff9acefc:82:02: Factory Sync Burst Adjust Size   16
Code: [Select]
30432>    Startup:ff9acf34:82:02: NTSC Sync 0x9471, 0x94719471
Could be a overlay ?
Code: [Select]
304BE>    Startup:ff9acfb4:82:02: Factory YUV Adjust Add  0x405c6f80
304ED>    Startup:ff9acfc8:82:02: Factory YUV Adjust Size 24
I was puzzled at first , but I think TFT YUV is full range & of course NTSC YUV is clamp to 16-235 (bt-601 & rec709) and that would feed to the HDMI as per protocol .
 
Code: [Select]
30511>    Startup:ff9acfe8:82:02: TFT  Y   0x80, 0x80
30554>    Startup:ff9ad004:82:02: TFT  UV  0x8080, 0x8080
30587>    Startup:ff9ad020:82:02: NTSC Y   0x35, 0x35
305AD>    Startup:ff9ad03c:82:02: NTSC UV  0x2d42, 0x2d42
For why I'm doing this so I can understand all the systems better .


reddeercity

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Re: 5D2 dm-log files for R&D
« Reply #8 on: February 10, 2018, 03:21:18 AM »
Reading thought my decompiled rom from 5d2 for some useful information , found this
Code: [Select]
ff0316b4 FramTable == NULL
ff031b47 @DP_SetCroppingFrameLocation(X:%d Y:%d W:%d H:%d)
ff031b7c BaseW:%d BaseH:%d Angle:%d
ff031b9f @DP_SetCroppingFrameLocation FrameSize Exchange To HDMI
ff031bd8 Angle == 3600
so there a "frame table" the other thing I find very interesting specially for UHD is "SetCroppingFrameLocation FrameSize Exchange To HDMI"
could this be modified for correct framing for UHD/4k being
max output  HDMI#Version_1.3a (5d2 D4 ,more then likely D5 too) is 1920 × 1080 at 120 Hz or 2560 × 1440 at 60 Hz plus deep color (16bit) & XvYCC extended Gamut  .
It must do this already when in video mode with liveview FF in HD , be nice not to have the center crop in hdmi with 3x crop greater then 1080p up to 2.5k.

reddeercity

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  • Posts: 1636
Re: 5D2 - QEMU & DM Log files for R&D
« Reply #9 on: July 20, 2018, 06:59:13 AM »
I do have the emulater Qemu up and running now so I can continue on working on digic IV cams (5d2 , 50d, 7d)
Found some interesting Info in my  MMIO activity (registers) and interrupts Log from qemu
7D stuff in the 5d2 ROM ? , wait it get better .
Code: [Select]
[GPIO]         at 0x001035F4:C0221000 [0xC0220024] <- 0x48      : GPIO_9 (master woke up on 7D)600d , go figure
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[GPIO]         at 0x001035F4:C0221000 [0xC02200DC] <- 0x4C      : GPIO_55 (abort situation for FROMUTIL on 600D)really 1000d ?
Code: [Select]
[GPIO]         at 0x001035F4:C0221000 [0xC022012C] <- 0x4C      : GPIO_75 (1000D display)Some more good stuff -- CF/SD card
Code: [Select]
[GPIO]         at 0x001033D0:00103618 [0xC022301C] <- 0x20      : CF/SD detect
[GPIO]         at 0x001033D4:00103618 [0xC022301C] -> 0x0       : CF/SD detect

***would this be the clocking for the CF card?***
[BASIC]        at 0x0010341C:00103618 [0xC0400008] -> 0x1010001 : CLOCK_ENABLE: ??? ??? DMA0
[BASIC]        at 0x00103424:00103618 [0xC0400008] <- 0x1010041 : CLOCK_ENABLE: ??? ??? ??? DMA0


[GPIO]         at 0x00102494:001000A0 [0xC022301C] -> 0x0       : CF/SD detect
[GPIO]         at 0x0010250C:00102500 [0xC0220074] <- 0x46      : GPIO_29
[GPIO]         at 0x0010251C:00102518 [0xC0220074] <- 0x44      : GPIO_29
[CFATA]        at 0x00102530:0010252C [0xC0608104] -> 0x4       : CFDMA ready maybe?
[GPIO]         at 0x00102540:0010252C [0xC0220074] <- 0x46      : GPIO_29
[GPIO]         at 0x00102550:00102550 [0xC0220074] <- 0x44      : GPIO_29
[CFATA]        at 0x00102560:00102560 [0xC0608104] -> 0x4       : CFDMA ready maybe?

Timer Stuff or is this the timing for CF card ? I remember a1ex tell me in a post that the CF card on 5D2 can be over clocked
could this be useful ?
Code: [Select]
[BASIC]        at 0x00103FD0:00800D8C [0xC0400008] -> 0x1010001 : CLOCK_ENABLE: ??? ??? DMA0
[BASIC]        at 0x00103FE0:00800D8C [0xC0400008] <- 0x1210503 : CLOCK_ENABLE: ??? LCLK PWM Tmr0 ??? SIO DMA0
TIMER]        at 0x00103BD4:00000000 [0xC0210000] <- 0x80000000: Timer #0: stopped
[TIMER]        at 0x00103BD8:00000000 [0xC0210000] <- 0x0       : Timer #0: stopped
[TIMER]        at 0x00103BE0:00000000 [0xC0210004] <- 0x2       : ???
[TIMER]        at 0x00103BE8:00000000 [0xC0210008] <- 0xFFFFFFFF: Timer #0: will trigger after 4294967 ms
[TIMER]        at 0x00103BF4:00000000 [0xC0210010] <- 0x1       : Timer #0: interrupt enable?
[TIMER]        at 0x00103BFC:00000000 [0xC0210014] <- 0x0       : ???
[TIMER]        at 0x00103C10:00105F4C [0xC0210000] <- 0x1       : Timer #0: starting
[*unk*]        at 0x0010602C:00105F50 [0xC0238080] <- 0x0       : ???
[TIMER]        at 0x00103704:00103720 [0xC021000C] -> 0x0       : Timer #0: current value
[TIMER]        at 0x00103704:00103728 [0xC021000C] -> 0x100     : Timer #0: current value

[TIMER]        at 0x00103704:00103720 [0xC021000C] -> 0x200     : Timer #0: current value
[TIMER]        at 0x00103704:00103728 [0xC021000C] -> 0x200     : Timer #0: current value
[TIMER]        at 0x00103704:00103728 [0xC021000C] -> 0x200     : Timer #0: current value
[TIMER]        at 0x00103704:00103728 [0xC021000C] -> 0x200     : Timer #0: current value
[TIMER]        at 0x00103704:00103728 [0xC021000C] -> 0x200     : Timer #0: current value
[TIMER]        at 0x00103704:00103728 [0xC021000C] -> 0x200     : Timer #0: current value
[TIMER]        at 0x00103704:00103728 [0xC021000C] -> 0x200     : Timer #0: current value
[TIMER]        at 0x00103704:00103728 [0xC021000C] -> 0x200     : Timer #0: current value
[TIMER]        at 0x00103704:00103728 [0xC021000C] -> 0x200     : Timer #0: current value
[TIMER]        at 0x00103704:00103728 [0xC021000C] -> 0x300     : Timer #0: current value
TX register
Code: [Select]
[GPIO]         at 0x00105938:00105548 [0xC0220028] <- 0x44      : GPIO_10
[SIO1]         at 0x0010593C:00105548 [0xC0820118] <- 0x0       : TX register
[SIO1]         at 0x00105940:00105548 [0xC0820104] <- 0x1       : Transmit: 0x00000000, setup 0x800EFF11 0x00000000 0x00000111 PC: 0x00105940
[SIO1]         at 0x00105944:00105548 [0xC0820104] -> 0x0       
[GPIO]         at 0x00105954:00105548 [0xC0220028] <- 0x46      : GPIO_10
[GPIO]         at 0x0010596C:00105548 [0xC0220020] <- 0x48      : GPIO_8