UHS-I / SD cards investigation

[theBilalFakhouri]

Yes, this register 0xC040060C has no effect, in this preset all the values are the default ones from Canon, except 0xC0400600, it's original value is 0x3, by tweaking it to 0x8 gives the 192 MHz Preset, without doing any another changes.

[Danne]

Yes, it's probably not used so disables that reg. Made 240Mhz work giving same write speed as 192Mhz. 160Mhz patch won't work with this.

[Danne]

Maybe we should look into:
https://bitbucket.org/hudson/magic-lantern/src/sd_uhs/modules/sd_uhs/sd_uhs.c#lines-59
drv_strength

Also note, if this isn´t applied:

Code: [Select]

    /* enable SDR104 */
    //patch_hook_function(sd_set_function, MEM(sd_set_function), sd_set_function_log, "SDR104");
    //SD_ReConfiguration();
We can skip this:

Code: [Select]

//static void sd_set_function_log(uint32_t* regs, uint32_t* stack, uint32_t pc)
//{
  //  qprintf("sd_set_function(0x%x)\n", regs[0]);
   
    /* UHS-I SDR50? */
    //if (regs[0] == 0xff0002)
    //{
        /* force UHS-I SDR104 */
      //  regs[0] = 0xff0003;
   // }
// }
EDIT:
Also, basically what is needed for the eosm is this(reduced the code):

Code: [Select]

/**
 * Experimental SD UHS overclocking.
 */

#include <module.h>
#include <dryos.h>
#include <patch.h>
#include <console.h>
#include <config.h>
#include <lens.h>

/* camera-specific parameters */
static uint32_t sd_setup_mode = 0;
static uint32_t sd_setup_mode_in = 0;
static uint32_t sd_setup_mode_reg = 0xFFFFFFFF;
static uint32_t sd_set_function = 0;

static uint32_t uhs_regs[]     = { 0xC0400600, 0xC0400604,/*C0400608, C040060C*/0xC0400610, 0xC0400614, 0xC0400618, 0xC0400624, 0xC0400628, 0xC040061C, 0xC0400620 };   /* register addresses */
static uint32_t sdr_160MHz[]   = {        0x2,        0x2,                             0x1, 0x1D000001,        0x0,      0x100,      0x100,      0x100,        0x1 };   /* overclocked values: 160MHz = 96*(4+1)/(2?+1) (found by brute-forcing) */
static uint32_t sdr_192MHz[]   = {        0x8,        0x3,                             0x4, 0x1D000301,        0x0,      0x201,      0x201,      0x100,        0x4 };
static uint32_t sdr_240MHz[]   = {        0x8,        0x3,                             0x3, 0x1D000301,        0x0,      0x201,      0x201,      0x100,        0x3 };

static uint32_t uhs_vals[COUNT(uhs_regs)];  /* current values */
static int sd_setup_mode_enable = 0;
static int turned_on = 0;
static CONFIG_INT("sd.sd_overclock", sd_overclock, 2);

/* start of the function */
static void sd_setup_mode_log(uint32_t* regs, uint32_t* stack, uint32_t pc)
{
    qprintf("sd_setup_mode(dev=%x)\n", regs[0]);
   
    /* this function is also used for other interfaces, such as serial flash */
    /* only enable overriding when called with dev=1 */
    sd_setup_mode_enable = (regs[0] == 1);
}

/* called right before the case switch in sd_setup_mode (not at the start of the function!) */
static void sd_setup_mode_in_log(uint32_t* regs, uint32_t* stack, uint32_t pc)
{
    qprintf("sd_setup_mode switch(mode=%x) en=%d\n", regs[sd_setup_mode_reg], sd_setup_mode_enable);
   
    if (sd_setup_mode_enable && regs[sd_setup_mode_reg] == 4)   /* SDR50? */
    {
        /* set our register overrides */
        for (int i = 0; i < COUNT(uhs_regs); i++)
        {
            MEM(uhs_regs[i]) = uhs_vals[i];
        }
       
        /* set some invalid mode to bypass the case switch
         * and keep our register values only */
        regs[sd_setup_mode_reg] = 0x13;
    }
}

static void sd_overclock_task()
{
   
    /* install the hack */
    if (sd_overclock == 1) memcpy(uhs_vals, sdr_160MHz, sizeof(uhs_vals));
    if (sd_overclock == 2) memcpy(uhs_vals, sdr_192MHz, sizeof(uhs_vals));
    if (sd_overclock == 3) memcpy(uhs_vals, sdr_240MHz, sizeof(uhs_vals));
    patch_hook_function(sd_setup_mode, MEM(sd_setup_mode), sd_setup_mode_log, "SD UHS");
    patch_hook_function(sd_setup_mode_in, MEM(sd_setup_mode_in), sd_setup_mode_in_log, "SD UHS");

}

static struct menu_entry sd_uhs_menu[] =
{
    {
        .name   = "sd overclock",
        .priv   = &sd_overclock,
        .max    = 3,
        .choices = CHOICES("OFF", "160MHz", "192MHz", "240MHz(feeling lucky)"),
        .help   = "Select a patch and restart camera. Disable with OFF and restart",
        .help2  = "Proven working with 95Mb/s and 170Mb/s cards",
    }
};

static struct menu_entry sd_uhs_menu1[] =
{
    {
        .name   = "sd overclock",
        .priv   = &sd_overclock,
        .max    = 3,
        .choices = CHOICES("OFF", "160MHz", "192MHz", "240MHz (feeling lucky)"),
        .help   = "Select a patch and restart camera. Disable with OFF and restart",
        .help2  = "Proven working with 95Mb/s and 170Mb/s cards",
    }
};

static unsigned int sd_uhs_init()
{
   
    //needed with manual lenses cause it stalls liveview. Maybe helps for cams like 6D. To be tested.
    while (is_movie_mode() && !lv)
    {
        msleep(100);
    }
   
    if (is_camera("EOSM", "2.0.2"))
    {
        sd_setup_mode       = 0xFF338D40;
        sd_setup_mode_in    = 0xFF338DC8;
        sd_setup_mode_reg   = 1;
        sd_set_function     = 0xFF63EF60;
        if (sd_overclock)
        {
            sd_overclock_task();
            turned_on = 1;
        }
    }
   
    menu_add("Movie", sd_uhs_menu, COUNT(sd_uhs_menu));
    menu_add("Debug", sd_uhs_menu1, COUNT(sd_uhs_menu1));
   
    return 0;
}

static unsigned int sd_uhs_deinit()
{
    return 0;
}

MODULE_INFO_START()
MODULE_INIT(sd_uhs_init)
MODULE_DEINIT(sd_uhs_deinit)
MODULE_INFO_END()

MODULE_CONFIGS_START()
MODULE_CONFIG(sd_overclock)
MODULE_CONFIGS_END()

[Bender@arsch]

Because of the 131mb/s writespeed limit, I tested just for fun the full resolution mode (5d3, 5784x3254 7,4fps at 10bit) with card spanning and the 160mhz module.

writspeed:
CF: 105MB/s, 42% idle
SD: 65MB/s, 12% idle

=170MB/s with green icon

[Danne]

Hehe, not bad! Reduced fps maximizes card speed.

[70MM13]

doesn't this point to cpu overhead within the magic lantern code?
slower fps reduces the burden on the cpu, no?
it would be great to know where the most cpu resources are going during usage.  is there a way to measure this, akin to "process explorer" in windows that shows exactly how much cpu resources are being used by each running process?

[Bender@arsch]

OK I think this is a failure:
3840x1440 x 23,976fps = ~130 mega pixel
5784x3254 x 7,4fps = ~140 mega pixel

I need ~125mb/s for 4K at 10bit, so 170mb/s is not correct I think.

[70MM13]

hopefully the write speed indicator is a true readout of the rate of data being written to the cards.

[Bender@arsch]

OK, I checked it out:
~1600mb (cf 830, sd 768), 102
frames =~14sec
1600/14 =114mb/s

[70MM13]

can you try the same comparison between rates that are reported versus recorded with both full sensor recording and cropped modes?  let's see if the same discrepancy exists...

[Bender@arsch]

Ok. Here are some short tests:

Full res. 5784x3254 7,4fps 10bit
CF: 105 42% idle
SD: 65 12%idle
=170MB/s
-> 1600 (cf 830, sd 768), 102 frames =~14sec
1600/14 =114mb/s

4K 3840x1536 23,976fps 10bit
CF: 70,4, 2% idle
SD: 50,4 6% idle
=120,8MB/s
-> 2791 (cf 1619, sd 1172), 558 frames =~23sec
2791/23 =121,3mb/s

4K half 4096x2304 11,988fps 10bit
CF: 108   22% idle
SD: 61,5 80% idle
=169,5MB/s
-> 1531 (cf 1340, sd 197), 191 frames =~16sec
1531/16 =95,6mb/s

Anamorphic 1808x2300 23,976fps 10bit
CF: 93 30% idle
SD: 53 66% idle
=146MB/s
-> 1397 (cf 1039, sd 358), 401 frames =~17sec
1397/17 =82,17mb/s

Anamorphic 1808x2300 23,976fps 12bit
CF: 90 30% idle
SD: 53 50% idle
=143MB/s
-> 1271 (cf 910, sd 361), 334 frames =~14sec
1271/14 =90,7mb/s

Anamorphic 1808x2300 23,976fps 14bit
CF: 77 15% idle
SD: 53 20% idle
=130MB/s
-> 1714 (cf 991, sd 723), 388 frames =~16sec
1714/16 =107mb/s

[70MM13]

well, isn't that interesting!

looks like we need to stick to only one preset for accurate speed reporting during recording...

hopefully someone familiar with the codebase can figure out what's going on!

nice catch...