JPCORE Hacking 4:2:2?

[ilguercio]

It's not a new connector, it looks unsoldered on your board

That's what i meant. The board of the second picture should be of a more recent batch as the serial number says.
Wonder why the latter has that connector and what it does while my board doesn't have it.

[nanomad]

If it is not connected to anything it is probably used during the assembly, maybe to upgrade the firmware of some component

[g3gg0]

to be honest...
i am quite sure those FPGAs seen on some older models dont have to do anything with MPEG encoding.
to me it looks as if the FPGA is for managing access to the external memory bus, maybe SDRAM controller, maybe HDMI interface etc.

but for H.264 encoding, the XA3S250E has far to few processing power.
the IP core you mentioned needs ~8k slices for NTSC/PAL videos. this FPGA has less than 2.5k.
for 720p we would need a virtex-4 instead of a spartan-3E and ~9k slices.

i am sure the digic has some built-in asic for mpeg encoding.

[1%]

It is possible its a memory controller as you're right it isn't that powerful. The other people's encoder claims better specs but they said soon for spartan 3.  The referenced one is also CABC

One way to check for sure is to look at those bins and see if the contents is there and if its encoder settings or memory settings.

Why is TMS320DM36x from TI mentioned in data sheets? IF the ASIC is on the digic chip can it be set to a different profile?

Is our encoder CABAC or CAVLC? One of them needs less CPU I think.

[g3gg0]

One way to check for sure is to look at those bins and see if the contents is there and if its encoder settings or memory settings.

Why is TMS320DM36x from TI mentioned in data sheets? IF the ASIC is on the digic chip can it be set to a different profile?

which binaries do you mean?
in which datasheets is the TMS320 mentioned?

br,
g3gg0

[1%]

http://magiclantern.wikia.com/wiki/Datasheets

Mentions that IC which does multi format. You're right tho, that spartan is not very powerful. 65nm process on digic has  alot of room but encoding is still requested from something.

    5d2: K218cfg.bin written at 0xF8760000 in Flash. See CHDK forum
    50d: K261cfg.bin written at 0xF8760000

600D, fpga is gone but mystery chip appears:

http://images.wikia.com/magiclantern/images/1/1f/600D-PCB2.jpg

Looked some more in the firmware, engine writes are used for encoder control?

H264E SetParameterH264Encode PassNo:%d'

Are there multiple passes?

JP62_OPCR_OPINPROG_BITON

This bit is set on. Original Program clock reference

Does this display read/write address of H264 stream?

DryosDebugMsg(0x1a, 0x1, 'H264E RequestH264EncHD r:%#lx,w:%#lx', ret_AJ_something_0xC0F26008_0xC0F04008_FF1C8D6C) => ret_DryosDebugMsg_FF1C8D84
AJ_fIDChecker_n_Eng_IO(0x1) => ret_AJ_fIDChecker_n_Eng_IO_FF1C8D8C


From reading that function it seems Jpeg data is being fed to it vs yuv??

I see:
'H264E JpegEncodeCompleteCallback EncodeSize:%#lx'


Some more interesting stuff, yes probably debug messages:

[JPCORE] SetEncodeH264Parameter P %d,%d,%d'
FF1E3494:   STRING: '[JPCORE] SetEncodeH264Parameter I %d,%d,%d'   
FF1E34C0:   STRING: '[JPCORE] JP62_SLCR1 P %d,%d,%d'

'[JPCORE] SetEncodeH264Parameter 0 %d,%d,%d'


Jpcore:

*'[JPCORE] JP62_SIZER %#lx'
*'[JPCORE] JP62_SEQCR1 %#lx'
*'[JPCORE] JP62_PICCR1 %#lx'
'[JPCORE] JP62_MISCR %#lx'
'[JPCORE] H264_SPS_PPS JP62_OPMR3 %#lx'
*'[JPCORE] JP62_OPMR3 %#lx'
[JPCORE] JP62_SLCR1 %#lx'
*'[JPCORE] JP62_SLCR2 %#lx'

Maybe we should monitor these values and see what they say when changing video modes/sizes. They should all be related to the encode... but then how do you change them? Does canon set this all at startup or at every movie start?

[1%]

How does TI DMS320DM368 address map compare to Digic? TI chip has similar features, including face detection, etc.






I know arm chip is slightly crappier.... it is a 926

Voice codec is mentioned in 600D firmware and docs for DMS320

[g3gg0]

600D, fpga is gone but mystery chip appears:

which chip do you mean?

[g3gg0]

not only the register map differs, but also the meaning of the registers are totally different.
e.g. setting GPIOs or configuring timers is done in a different way as on TMS320

[1%]

Hehehe, it was worth a shot, wonder where the idea came from then.. I mean the chip near the digic that looks like the package got cut off. with "hologram" on top.


Also, how do I turn these messages on so they show up in the log?

SetEncodeH264Parameter P %d,%d,%d'
JP62_SLCR1 P %d,%d,%d'

I found this in tramell's old posts

        // increase jpcore debugging
        dm_set_store_level( 0x15, 2 );
       dm_set_store_level( 0x2f, 0x16 );


My buffer dies quick but these are the logs produced.

More engio info than jpgocre info it seems. I think its movie being encoded step by step or at least part of that process.

http://www.qfpost.com/file/d?g=4urpVluQh

[1%]

Made a couple more logs.

MVR stop at 30 minutes:

Code Select Expand


311: 45595.878 [MR] mvrRecStop
314: 45600.815 [LV] [PATH] GetPathDriveInfo[10]
315: 45792.921 [MR_MOV] Write : End(19) (21156KB/S)
317: 46043.111 [MR] mvrRecStopped
318: 46043.185 [MR] mvrRecStopped : FreeMemoryResourceForMovieRecWork
319: 46043.498 [MR] mvrRecStopped : End:91905b60



A peep from JPCORE

663448: 36277.602 [ENG] [JPCORE] ERROR Invalid beta 7

Logs:
http://www.qfpost.com/file/d?g=UKLVFiXSJ
http://www.qfpost.com/file/d?g=lxrRIu9Oe

[Indy]

Hi,

see http://magiclantern.wikia.com/wiki/Register_Map/550D
jpec IC section
see http://magiclantern.wikia.com/wiki/ASM_Dictionary
DEC, JPE...

the ML Wiki contains a lot of information, use its search engine

Indy