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I seem to recall CHDK / srsa already knew this, from some other thread, but I couldn't find it and there were no details.

There was some discussion in https://chdk.setepontos.com/index.php?topic=13773.10

I've only confirmed this on 200D.  I'd expect all Digic 7 and 8 to be similar.  Maybe the dual processor Digic 4, 5 and 6 will use a similar API?  Maybe not.

AFAIK the earlier "dual digic" ran a separate firmware on each CPU, see https://magiclantern.fandom.com/wiki/7D_internals and https://web.archive.org/web/20130309115612/http://www.magiclantern.fm/whats-new/104-releases/140-first-7d-alpha-released

Single Digic 6 (on P&S at least) has a somewhat similar situation: "Omar" is another Cortex R4, similar but not identical to the main core, which runs its own stripped down instance of DryOS. It's not too hard to run code there, but obviously synchronization would be more complicated https://chdk.setepontos.com/index.php?topic=11316.msg119473#msg119473

FWIW, I wrote some ghidra scripts for CHDK that may have useful bits for ML development too.

set_tmode_reg_at from http://subversion.assembla.com/svn/chdk/trunk/tools/ghidra_scripts/chdklib/analyzeutil.py can be used to set the arm/thumb state on an address before disassembling.

http://subversion.assembla.com/svn/chdk/trunk/tools/ghidra_scripts/CleanThumb2BookmarkErrors.py iterates over Ghidra generated error bookmarks and attempts to fix some common issues I noticed working with thumb2 firmware.

I also wrote some notes on using the version tracking tool, which I've found very useful for porting: https://chdk.setepontos.com/index.php?topic=13718.msg142082#msg142082