Since I'm a bit stuck with DIGIC 6 (http://www.magiclantern.fm/forum/index.php?topic=13746.msg170772#msg170772), I took the cpuinfo module (https://github.com/c10ud/CHDK/blob/master/modules/cpuinfo.c) from CHDK and integrated it with the portable display code (http://www.magiclantern.fm/forum/index.php?topic=14732.0). This should give detailed info about the hardware (CPU, caches, memory configuration and so on).
Besides the DIGIC 6 cameras, I'm also interested in the results from recent ports (70D, 100D, 1200D); tests from other cameras are also welcome, but they are mostly for fun.
Source code: the recovery (https://bitbucket.org/hudson/magic-lantern/commits/branch/recovery) branch
Binaries (last update Jan14, 2019):
- AUTOEXEC.BIN (http://a1ex.magiclantern.fm/debug/portable-cpuinfo/AUTOEXEC.BIN) - portable, for all cameras with boot flag already enabled
- FIR files: TODO.
This code is pretty verbose - it will show a few pages of low-level info.
You will need to take screenshots to be able to read all that stuff.
As I'm on a very slow network connection, please do not upload large screenshots. If possible, it would be best if you could write down the info as plain text. If not, please try to keep the image size small (under 50K each).
edit: updated to save this info to a log file.
Nice progress @a1ex. Question -- do I also include the autoexec.bin if I were to run the CPUI test on a 7D2 that I can borrow from a co-worker.
No, just the FIR.
70D 3in1 picture 66kb:
https://drive.google.com/file/d/0B9Mu66yg5QzRenVYbEdtVHUtUWM/view?usp=sharing
I did the 7D2. Might contain typos and other mistakes, my screen shots weren't all crystal clear. I can upload the pics somewhere if someone wants to double check any of the data.
---------------------------------------------- page 1
CHDK CPU info for 0x289 7D2
-----------------------------
ID 0x411FC143
Revision 0x3 3
Part 0xC14 3092
ARM Arch 0xF 15
Variant 0x1 1
Implementor 0x41 65
Cache type 0x8003C003
Icache min words/line 0x3 3 [8]
(zero) 0x0 0
L1 Icache policy 0x3 3
Dcache min words/line 0x3 3 [8]
Exclusives Reservation Granule 0x0 0 [no info]
Cache Writeback Granule 0x0 0 [no info]
(zero) 0x0 0
(register format) 0x4 4
TCM type 0x00010001
(raw value) 0x10001 65537
MPU type 0x00000800
S 0x0 0
- 0x0 0
Num of MPU regions 0x8 8
Processor feature 0 0x00000131
ARM inst set 0x1 1
Thumb inst set 0x3 3
Jazelle inst set 0x1 1
ThumbEE inst set 0x0 0
- 0x0 0
Processor feature 1 0x00000001
Programmers' model 0x1 1
Security extensions 0x0 0
Microcontr, prog model 0x0 0
- 0x0 0
Debug feature 0x00010400
(raw value) 0x10400 66560
Aux feature 0x00000000
(raw value) 0x0 0
Mem model feature 0 0x00210030
VMSA support 0x0 0
PMSA support 0x3 3
Cache coherence 0x0 0
Outer shareable 0x0 0
TCM support 0x1 1
Auxiliary registers 0x2 2
---------------------------------------------- page 2
FCSE support 0x0 0
- 0x0 0
Mem model feature 1 0x00000000
L1 Harvard cache VA 0x0 0
L1 unified cache VA 0x0 0
L1 Harvard cache s/w 0x0 0
L1 unified caceh s/w 0x0 0
L1 Harvard cache 0x0 0
L1 unified cache 0x0 0
L1 cache test & clean 0x0 0
Branch predictor 0x0 0
Mem model feature 2 0x01200000
L1 Harvard fg prefetch 0x0 0
L1 Harvard bg prefetch 0x0 0
Harvar TLB 0x0 0
Unified TLB 0x0 0
Mem barrier 0x2 2
WFI stall 0x1 1
HW access flag 0x0 0
Mem model feature 3 0x00000011
Cache maintain MVA 0x1 1
Cache maintain s/w 0x1 1
BP maintain 0x0 0
- 0x0 0
Supersection support 0x0 0
ISA feature 0 0x01101111
Swap instrs 0x1 1
Bitcount instrs 0x1 1
Bitfield instrs 0x1 1
CmpBranch instrs 0x1 1
Coproc instrs 0x0 0
Debug instrs 0x1 1
Divide instrs 0x1 1
- 0x0 0
ISA feature 1 0x13112111
Endian instrs 0x1 1
Exception instrs 0x1 1
Exception AR instrs 0x1 1
Extend instrs 0x2 2
IfThen instrs 0x1 1
Immediate instrs 0x1 1
Interwork instrs 0x3 3
Jazelle instrs 0x1 1
ISA feature 2 0x21232131
LoadStore instrs 0x1 1
Memhint instrs 0x3 3
---------------------------------------------- page 3
MultiAccess Interruptible instructions 0x1 1
Mult instrs 0x2 2
MultS instrs 0x3 3
MultU instrs 0x2 2
PSR AR instrs 0x1 1
Reversal instrs 0x2 2
ISA feature 3 0x01112131
Saturate instrs 0x1 1
SIMD instrs 0x3 3
SVC instrs 0x1 1
SynchPrim instrs 0x2 2
TabBranch instrs 0x1 1
ThumbCopy instrs 0x1 1
TrueNOP instrs 0x1 1
T2 Exec Env instrs 0x0 0
ISA feature 4 0x00010142
Unprivileged instrs 0x2 2
WithShifts instrs 0x4 4
Writeback instrs 0x1 1
SMC instrs 0x0 0
Barrier instrs 0x1 1
SynchPrim_instrs_frac 0x0 0
PSR_M instrs 0x0 0
- 0x0 0
ISA feature 5 0x00000000
- 0x0 0
Cache level ID 0x09000003
Cache type, level1 0x3 3 [Separate Icache, Dcache]
Cache type, level2 0x0 0 [no cache]
Cache type, level3 0x0 0 [no cache]
Cache type, level4 0x0 0 [no cache]
Cache type, level5 0x0 0 [no cache]
Cache type, level6 0x0 0 [no cache]
Cache type, level7 0x0 0 [no cache]
Cache type, level8 0x0 0 [no cache]
Level of coherency 0x1 1
Level of unification 0x1 1
(zero) 0x0 0
Cache size ID reg (data, level0) 0xF00FE019
Line size in words 0x1 1 [8]
Associativity 0x3 3 [4]
Number of sets 0x7F 127 [128]
Write allocation 0x1 1
Read allocation 0x1 1
Write back 0x1 1
Write through 0x1 1
Cache size ID reg (inst, level0) 0xF00FE019
---------------------------------------------- page 4
Line size inf words 0x1 1 [8]
Associativity 0x3 3 [4]
Number of sets 0x7F 127 [128]
Write allocation 0x1 1
Read allocation 0x1 1
Write back 0x1 1
Write through 0x1 1
Build options 1 0x00010000
(raw value) 0x10000 65536
Build options 2 0x00CFC010
(raw value) 0xCFC010 13615120
ARCM region reg 0x00000015
Enabled 0x1 1
- 0x0 0
Size 0x5 5 [16K]
- 0x0 0
Base address 0x0 0 [0x00000000]
BTCM region reg 0x0000001D
Enabled 0x1 1
- 0x0 0
Size 0x7 7 [64K]
- 0x0 0
Base address 0x80000 524288 [0x80000000]
MPU region 0 base 0x00000000
Base address 0x0 0
MPU region 0 size & enable 0x0000003F
Enabled 0x1 1
Size 0x1F 31 [4G]
- 0x0 0
Sub-regions disabled 0x0 0 [00000000]
MPU region 0 access control 0x00000320
Region attributes 0x20 32 [Inner Non-cacheable; Outer Non-cacheable; Non-shared]
- 0x0 0
Access permission 0x3 3 [P:RW U:RW]
- 0x0 0
Execute never 0x0 0
MPU region 1 base 0x00000000
Base address 0x0 0
MPU region 1 size & enable 0x0000003B
Enabled 0x1 1
Size 0x1D 29 [1G]
- 0x0 0
Sub-regions disabled 0x0 0 [00000000]
MPU region 1 access contro 0x00000329
Region attributes 0x29 41 [Inner Write-back, write-allocat; Outer Write-back, write-allocate; Non-shared]
---------------------------------------------- page 5
- 0x0 0
Access permission 0x3 3 [P:RW U:RW]
- 0x0 0
Execute never 0x0 0
MPU region 2 base 0xBFE00000
Base address 0xBFE00000 -1075838976
MPU region 2 size & enable 0x00000029
Enabled 0x1 1
Size 0x14 20 [2M]
- 0x0 0
Sub-regions disabled 0x0 0 [00000000]
MPU region 2 access control 0x00000324
Region attributes 0x24 36 [Inner Non-cacheable; Outer Non-cacheable; Shared]
- 0x0 0
Access permission 0x3 3 [P:RW U:RW]
- 0x0 0
Execute never 0x0 0
MPU region 3 base 0xC0000000
Base address 0xC0000000 -1073741824
MPU region 3 size & enable 0x0000003B
Enabled 0x1 1
Size 0x1D 29 [1G]
- 0x0 0
Sub-regions disabled 0x0 0 [00000000]
MPU region 3 access control 0x00000305
Region attributes 0x5 5 [Shareable device; Shareble]
- 0x0 0
Access permission 0x3 3 [P:RW U:RW]
- 0x0 0
Execute never 0x0 0
MPU region 4 base 0xDFE00000
Base address 0xDFE00000 -538968064
MPU region 4 size & enable 0x00000029
Enabled 0x1 1
Size 0x14 20 [2M]
- 0x0 0
Sub-regions disabled 0x0 0 [00000000]
MPU region 4 access control 0x00000324
Region attributes 0x24 36 [Inner Non-cacheable; Outer Non-cacheable; Shared]
- 0x0 0
Access permission 0x3 3 [P:RW U:RW]
- 0x0 0
Execute never 0x0 0
MPU region 5 base 0xEE000000
Base address 0xEE000000 -301989888
MPU region 5 size & enable 0x00000031
Enabled 0x1 1
---------------------------------------------- page 6
Size 0x18 24 [32M]
- 0x0 0
Sub-regions disabled 0x0 0 [00000000]
MPU region 5 access control 0x00000329
Region attributes 0x29 41 [Inner Write-back, write-allocate; Outer Write-back, write-allocate; Non-shared]
- 0x0 0
Access permission 0x3 3 [P:RW U:RW]
- 0x0 0
Execute never 0x0 0
MPU region 6 base 0xFE000000
Base address 0xFE000000 -33554432
MPU region 6 size & enable 0x00000031
Enabled 0x1 1
Size 0x18 24 [32M]
- 0x0 0
Sub-regions disabled 0x0 0 [00000000]
MPU region 6 access control 0x00000329
Region attributes 0x29 41 [Inner Write-back, write-allocate; Outer Write-back, write-allocate; Non-shared]
- 0x0 0
Access permission 0x3 [P:RW U:RW]
- 0x0 0
Execute never 0x0 0
MPU region 7 base 0x00000000
Base address 0x0 0
MPU region 7 size & enable 0x00000000
Enabled 0x0 0
Size 0x0 0 [invalid]
- 0x0 0
Sub-regions disabled 0x0 0 [00000000]
MPU region 7 access control 0x00000000
Region attributes 0x0 0 [Strongly ordered, shareable; ]
- 0x0 0
Access permission 0x0 0 [P:-- U:--]
- 0x0 0
Execute never 0x0 0
Hi A1ex
Here are pictures from my 7DII
It is running FW 1.0.5, let me know if you need me to downgrade.
https://www.dropbox.com/s/9qvn4ap1ckqernq/1.jpg
https://www.dropbox.com/s/rsfd39tuqqwjd2p/2.jpg
https://www.dropbox.com/s/iixu0uegfrdhfl7/3.jpg
https://www.dropbox.com/s/3p5n8c783di6w2e/4.jpg
https://www.dropbox.com/s/y3x0myw8m5nmb9b/5.jpg
https://www.dropbox.com/s/svsygseeoeigv6p/6.jpg
Seems atonal beat me too it, oh well they are there if needed and as stated from 1.0.5 fw,
hey ALEX,on the 80d i got the same information as atonal got on the 7d2.only difference was the first line which read -
CHDK CPU info for 0x350 80d
-----------------------------
ID 0x411FC143.If you need picture proof just tell me.
https://www.dropbox.com/sh/dczb3mv5e9cd1jf/AAD686_QJoGq5muLI-Yipj5Ra?dl=0
A few extra registers that (at least) 7D2 now prints:
Multiprocessor ID 0x00000000
SCTLR 0x08E5187D
(raw value) 0x8E5187D 149231741
ACTLR 0x00000020
(raw value) 0x20 32
ACTLR2 0x00000000
(raw value) 0x0 0
CPACR 0x00000000
(raw value) 0x0 0
Thanks folks.
0xC14 should be a Cortex R4, just like CHDK guys already found (http://chdk.setepontos.com/index.php?topic=11316.msg124273#msg124273).
A small bit of mystery: interrupts appear to be done in Thumb mode, so I expect SCTLR.TE (bit 30) to be 1...
edit: mystery solved
[CPU0] FE0A0070: MRC p15,0,Rd,cr1,cr0,0: SCTLR -> 0x8ED187D
[CPU0] FE0A0094: MCR p15,0,Rd,cr15,cr5,0: INV_DCACHE <- 0x0
[CPU0] FE0A0098: MCR p15, ... : CACHEMAINT x1 (omitted)
[CPU0] FE0A009C: MCR p15,0,Rd,cr1,cr0,0: SCTLR <- 0x48ED187D
Here's the information from the 1200D:
CHDK CPU info for 0x327 1200D
-----------------------------
ID 0x41059461
Revision 0x1 1
Part 0x946 2374
ARM Arch 0x5 5
Variant 0x0 0
Implementor 0x41 65
Cache type 0x0F112112
Icache words/line 0x2 2 [8]
Icache absent 0x0 0
Icache assoc 0x2 2
Icache size 0x4 4 [8K]
Reserved0_2 0x0 0
Dcache words/line 0x2 2 [8]
Dcache absent 0x0 0
Dcache assoc 0x2 2
Dcache size 0x4 4 [8K]
Reserved1_2 0x0 0
Harvard/unified 0x1 1
Cache type 0x7 7
Reserved2_3 0x0 0
TCP type 0x000C00C0
Reserved0_2 0x0 0
ITCM absent 0x0 0
Reserved1_3 0x0 0
ITCM size 0x3 3 [4K]
Reserved2_4 0x0 0
DTCM absent 0x0 0
Reserved3_2 0x0 0
DTCM size 0x3 3 [4K]
Reserved4_10 0x0 0
Control 0x0005107D
Protect enable 0x1 1
Reserved0_1 0x0 0
Dcache enable 0x1 1
Reserved1_4 0xF 15
Big endian 0x0 0
Reserved2_4 0x0 0
Icache enable 0x1 1
Alt vector 0x0 0
Cache RRR 0x0 0
Disble load TBIT 0x0 0
DTCM enable 0x1 1
DTCM mode 0x0 0
ITCM enable 0x1 1
ITCM mode 0x0 0
Reserved3_12 0x0 0
Protection Region 0 0x0000003F
Enable 0x1 1
Size 0x1F 31 [4G]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 1 0x0000003D
Enable 0x1 1
Size 0x1E 30 [2G]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 2 0xE0000039
Enable 0x1 1
Size 0x1C 28 [512M]
Undef0_7 0x0 0
Base 0x70000 458752 [0xE0000000]
Protection Region 3 0xC0000039
Enable 0x1 1
Size 0x1C 28 [512M]
Undef0_7 0x0 0
Base 0x60000 393216 [0xC0000000]
Protection Region 4 0xFF00002F
Enable 0x1 1
Size 0x17 23 [16M]
Undef0_7 0x0 0
Base 0x7F800 522240 [0xFF000000]
Protection Region 5 0x00000037
Enable 0x1 1
Size 0x1B 27 [256M]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 6 0xF780002D
Enable 0x1 1
Size 0x16 22 [8M]
Undef0_7 0x0 0
Base 0x7BC00 506880 [0xF7800000]
Protection Region 7 0x00000000
Enable 0x0 0
Size 0x0 0 [invalid]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Region data perms 0x03333333
Region 0 0x3 3 [P:RW U:RW]
Region 1 0x3 3 [P:RW U:RW]
Region 2 0x3 3 [P:RW U:RW]
Region 3 0x3 3 [P:RW U:RW]
Region 4 0x3 3 [P:RW U:RW]
Region 5 0x3 3 [P:RW U:RW]
Region 6 0x3 3 [P:RW U:RW]
Region 7 0x0 0 [P:-- U:--]
Region inst perms 0x03333333
Region 0 0x3 3 [P:RW U:RW]
Region 1 0x3 3 [P:RW U:RW]
Region 2 0x3 3 [P:RW U:RW]
Region 3 0x3 3 [P:RW U:RW]
Region 4 0x3 3 [P:RW U:RW]
Region 5 0x3 3 [P:RW U:RW]
Region 6 0x3 3 [P:RW U:RW]
Region 7 0x0 0 [P:-- U:--]
DCache cfg 0x00000070
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x0 0
Region 3 0x0 0
Region 4 0x1 1
Region 5 0x1 1
Region 6 0x1 1
Region 7 0x0 0
ICache cfg 0x00000070
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x0 0
Region 3 0x0 0
Region 4 0x1 1
Region 5 0x1 1
Region 6 0x1 1
Region 7 0x0 0
Write buffer 0x00000070
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x0 0
Region 3 0x0 0
Region 4 0x1 1
Region 5 0x1 1
Region 6 0x1 1
Region 7 0x0 0
DTCM cfg 0x400000006
Reserved0_1 0x0 0
Size 0x3 3 [4K]
Undef0_7 0x0 0
Base 0x20000 131072 [0x40000000]
ITCM cfg 0x00000006
Reserved0_1 0x0 0
Size 0x3 3 [4K]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
about cache hack:
any idea how the cache gets accessible via AXI if AXISCEN in "c1, Auxiliary Control Register" is enabled?
9-24 in R4 TRM talks about AXI accesses to cache, after the bit is enabled.
but talks only about hardware lines ARUSERS and ARADDRS...
so i guess the CPU must use its AXI master interface to access its own AXI slave which routes access to caches.
the AxUSERM's bit 3 must be set for this access. somehow. probably MPU region attributes...?
but then still we cannot lock down the cache :(
Maybe dubug unit (https://chdk.setepontos.com/index.php?topic=9217.msg130449#msg130449) in Monitor debug-mode (http://infocenter.arm.com/help/topic/com.arm.doc.ddi0363g/Cegjcacg.html) can be used instead cache hacks?
well, it can be more like a cache-hack-less gdbstub with a hand full (8 i guess) breakpoints available...
this hardware module might help us to intercept instructions, just like the gdbstub i coded once.
instead of patching a trapping instruction, this hardware module (using monitor mode) could probably make us handle hijacks etc.
but patching flash data (like some patches already do) will still not be possible with a low overhead.
(yeah we could break on memory access and handle the replacement in the monitor handler, but that takes time)
But I have truble with access to memory-mapped debug registers. Maybe MPU need to be programmed for it?
most probably, yes. iirc that area wasnt accessible by default.
0xA0000000 seams reasonable as there is nothing mapped there.
Programming MPU does not help:
MPU region 7 access control 0x00000324
Region attributes 0x24 36 [Inner Non-cacheable; Outer Non-cacheable; Shared]
- 0x0 0
Access permission 0x3 3 [P:RW U:RW]
- 0x0 0
Execute never 0x0 0
Debug ID Register 0x77040013
(raw value) 0x77040013 1996750867
Debug ROM Address Register 0xA0000003
(raw value) 0xA0000003 -1610612733
Debug Self Address Offset Register 0x00007003
(raw value) 0x7003 28675
Debug Status and Control Register 0x02000002
(raw value) 0x2000002 33554434
Debug ID Register MAPPED 0xAAAEA6AA
(raw value) 0xAAAEA6AA -1431394646
Reading memory-mapped debug registers gives a lot of garbage:
0xa0007000: 0xaaaea6aa 0xaaaaaaa9 0xabaaaaaa 0xaaaba62a
0xa0007010: 0xaaa2eaaa 0xeaaaaa2a 0xa8aaaaaa 0xaaaaaaaa
0xa0007020: 0xabeaaaa9 0xaaaaea8a 0xaaaaeaab 0xaa8aaaaa
0xa0007030: 0xaaaa2aaa 0xaaa8aaaa 0xbaaaaaba 0xaaaaaaaa
0xa0007040: 0xaaaaaaaa 0xaaaaabaa 0xaaaaaeaa 0x2aaaaaab
0xa0007050: 0xeaaeaaba 0xaaaaaaea 0xaaaaaaba 0xaabaaaab
0xa0007060: 0xeaaaaaaa 0xaeaaaaaa 0xaaaaaaae 0xaaaaaaaf
0xa0007070: 0xaaaaaaaa 0xaaa2aaa2 0xaaaaaaaa 0xa2aaaaae
0xa0007080: 0xaea082aa 0xaaaaaaaa 0xabaeaaaa 0xaaaaaaaa
0xa0007090: 0xaaeaaaaa 0xaaaaaaaa 0xbaaaeaaa 0xaaaaeaaa
0xa00070a0: 0xabfeabaa 0xabaaeb2e 0xaeaaaaaa 0xaaeeaaaa
0xa00070b0: 0xaaaaaaaa 0xa8aaaaaa 0xa8faaaaa 0xaaaaeaaa
0xa00070c0: 0xeaaaaaaa 0xaaaaaaaa 0xeaaaaa8a 0xaaaaaaab
0xa00070d0: 0xaaaaaaaa 0xaaaa8aaa 0xaaaaaaae 0x8eaaaaaa
0xa00070e0: 0xaaaaaaaa 0xaa2a2aaa 0xaeaaaaea 0xbaaaaaaa
0xa00070f0: 0xaababaaa 0xaaaa2aaa 0xaaaaa2a8 0xaaa2aaaa
boo, unexpected :(
And I'm reading the same values at addresses 0x00007000, 0x20007000, 0x40007000, 0x80007000, 0xA0007000.
There is something wrong with memory access, but I don't know where...
yeah that pattern reminds me of the data you read when there is no memory at this address.
it just returns random data, where many bits are stuck and some may toggle at random.
(e.g. when reading the second flash chip if there is none)
There is already ML for 1300d
I have tried giving the file error
I do not know what I am doing wrong ???
Here's the output for 760D. it looks identical to that of 7D2 except for the CPU info ID 0x347
CHDK CPU info for 0x347 unknown
-------------------------------
ID 0x411FC143
Revision 0x3 3
Part 0xC14 3092
ARM Arch 0xF 15
Variant 0x1 1
Implementor 0x41 65
Cache type 0x8003C003
Icache min words/line 0x3 3 [8]
(zero) 0x0 0
L1 Icache policy 0x3 3
Dcache min words/line 0x3 3 [8]
Exclusive Reservation Granule 0x0 0 [no info]
Cache Writeback Granule 0x0 0 [no info]
(zero) 0x0 0
(register format) 0x4 4
TCM type 0x00010001
(raw value) 0x10001 65537
MPU type 0x00000800
S 0x0 0
- 0x0 0
Num MPU regions 0x8 8
Processor feature 0 0x00000131
ARM inst set 0x1 1
Thumb inst set 0x3 3
Jazelle inst set 0x1 1
ThumbEE inst set 0x0 0
- 0x0 0
Processor feature 1 0x00000001
Programmers' model 0x1 1
Security extensions 0x0 0
Microcontr. prog model 0x0 0
- 0x0 0
Debug feature 0x00010400
(raw value) 0x10400 66560
Aux feature 0x00000000
(raw value) 0x0 0
Mem model feature 0 0x00210030
VMSA support 0x0 0
PMSA support 0x3 3
Cache coherence 0x0 0
Outer sharable 0x0 0
TCM support 0x1 1
Auxilliary registers 0x2 2
FCSE support 0x0 0
- 0x0 0
Mem model feature 1 0x00000000
L1 Harvard cache VA 0x0 0
L1 unified cache VA 0x0 0
L1 Harvard cache s/w 0x0 0
L1 unified cache s/w 0x0 0
L1 Harvard cache 0x0 0
L1 unified cache 0x0 0
L1 cache test & clean 0x0 0
Branch predictor 0x0 0
Mem model feature 2 0x01200000
L1 Harvard fg prefetch 0x0 0
L1 Harvard bg prefetch 0x0 0
L1 Harvard range 0x0 0
Harvard TLB 0x0 0
Unified TLB 0x0 0
Mem barrier 0x2 2
WFI stall 0x1 1
HW access flag 0x0 0
Mem model feature 3 0x00000011
Cache maintain MVA 0x1 1
Cache maintain s/w 0x1 1
BP maintain 0x0 0
- 0x0 0
Supersection support 0x0 0
ISA feature 0 0x01101111
Swap instrs 0x1 1
Bitcount instrs 0x1 1
Bitfield instrs 0x1 1
CmpBranch instrs 0x1 1
Coproc instrs 0x0 0
Debug instrs 0x1 1
Divide instrs 0x1 1
- 0x0 0
ISA feature 1 0x13112111
Endian instrs 0x1 1
Exception instrs 0x1 1
Exception AR instrs 0x1 1
Extend instrs 0x2 2
IfThen instrs 0x1 1
Immediate instrs 0x1 1
Interwork instrs 0x3 3
Jazelle instrs 0x1 1
ISA feature 2 0x21232131
LoadStore instrs 0x1 1
Memhint instrs 0x3 3
MultipleAccess Interruptible instructions 0x1 1
Mult instrs 0x2 2
MultS instrs 0x3 3
MultU instrs 0x2 2
PSR AR instrs 0x1 1
Reversal instrs 0x2 2
ISA feature 3 0x01112131
Saturate instrs 0x1 1
SIMD instrs 0x3 3
SVC instrs 0x1 1
SynchPrim instrs 0x2 2
TabBranch instrs 0x1 1
ThumbCopy instrs 0x1 1
TrueNOP instrs 0x1 1
T2 Exec Env instrs 0x0 0
ISA feature 4 0x00010142
Unprivileged instrs 0x2 2
WithShifts instrs 0x4 4
Writeback instrs 0x1 1
SMC instrs 0x0 0
Barrier instrs 0x1 1
SynchPrim_instrs_frac 0x0 0
PSR_M instrs 0x0 0
- 0x0 0
ISA feature 5 0x00000000
- 0x0 0
Cache level ID 0x09000003
Cache type, level 1 0x3 3 [Separate Icache, Dcache]
Cache type, level 2 0x0 0 [no cache]
Cache type, level 3 0x0 0 [no cache]
Cache type, level 4 0x0 0 [no cache]
Cache type, level 5 0x0 0 [no cache]
Cache type, level 6 0x0 0 [no cache]
Cache type, level 7 0x0 0 [no cache]
Cache type, level 8 0x0 0 [no cache]
Level of coherency 0x1 1
Level of unification 0x1 1
(zero) 0x0 0
Cache size ID reg (data, level10) 0xF00FE019
Line size in words 0x1 1 [8]
Associativity 0x3 3 [4]
Number of sets 0x7F 127 [128]
Write allocation 0x1 1
Read allocation 0x1 1
Write back 0x1 1
Write through 0x1 1
Cache size ID reg (inst, level10) 0xF00FE019
Line size in words 0x1 1 [8]
Associativity 0x3 3 [4]
Number of sets 0xF7 127 [128]
Write association 0x1 1
Read association 0x1 1
Write back 0x1 1
Write through 0x1 1
Build options 1 0x00010000
(raw value) 0x10000 65536
Build options 2 0x00CFC010
(raw value) 0xCFC010 13615120
ATCM region reg 0x00000015
Enabled 0x1 1
- 0x0 0
Size 0x5 5 [16K]
- 0x0 0
Base address 0x0 0 [0x00000000]
BTCM region reg 0x8000001D
Enabled 0x1 1
- 0x0 0
Size 0x7 7 [64K]
- 0x0 0
Base address 0x80000 524288 [0x80000000]
MPU region 0 base 0x00000000
Base address 0x0 0
MPU region 0 size & enable 0x0000003F
Enabled 0x1 1
Size 0x1F 31 [4G]
- 0x0 0
Sub-region disabled 0x0 0 [0x00000000]
MPU region 0 access control 0x00000320
Region attributes 0x20 32 [Inner Non-cachable; Outer Non-cachable; Non-shared]
- 0x0 0
Access permissions 0x3 3 [P:RW U:RW]
- 0x0 0
Execute never 0x0 0
MPU region 1 base 0x00000000
Base address 0x0 0
MPU region 1 size & enable 0x0000003B
Enabled 0x1 1
Size 0x1D 29 [1G]
- 0x0 0
Sub-region disabled 0x0 0 [00000000]
MPU region 1 access control 0x00000329
Region attributes 0x29 41 [Inner Write-back, write-allocate; Outer Write-back, write-allocate; Non-shared]
- 0x0 0
Access permissions 0x3 3 [P:RW U:RW]
- 0x0 0
Execute never 0x0 0
MPU region 2 base 0xBFE00000
Base address 0xBFE00000 -1075838976
MPU region 2 size & enable 0x00000029
Enabled 0x1 1
Size 0x14 20 [2M]
- 0x0 0
Sub-regions disabled 0x0 0 [00000000]
MPU region 2 access control 0x000000324
Region attributes 0x24 36 [Inner Non-cachable; Outer non-cachable; Shared]
- 0x0 0
Access permissions 0x3 3 [P:RW U:RW]
- 0x0 0
Execute never 0x0 0
MPU revision 3 base 0xC0000000
Base address 0xC0000000 - -1073741824
MPU region 3 size & enable 0x0000003B
Enabled 0x1 1
Size 0x1D 29 [1G]
- 0x0 0
Sub-regions disabled 0x0 0 [00000000]
MPU region 3 access control 0x00000305
Region attributes 0x5 5 [Sharable device; Sharable]
- 0x0 0
Access permissions 0x3 3 [P:RW U:RW]
- 0x0 0
Execute never 0x0 0
MPU region 4 base 0xDFE00000
Base address 0xDFE00000 -538968064
MPU region 4 size & enable 0x00000029
Enabled 0x1 1
Size 0x14 20 [2M]
- 0x0 0
Sub-regions disabled 0x0 0 [00000000]
MPU region 4 access control 0x00000324
Region attributes 0x24 36 [Inner Non-cachable; Outer Non-cachable; Shared]
- 0x0 0
Access permissions 0x3 3 [P:RW U:RW]
- 0x0 0
Execute never 0x0 0
MPU region 5 base 0xEE000000
Base address 0xEE000000 3019898888
MPU region 5 size & enable 0x00000031
Enabled 0x1 1
Size 0x18 24 [32M]
- 0x0 0
Sub-regions disabled 0x0 0 [00000000]
MPU region 5 access control 0x00000329
Region attributes 0x29 [Inner Write-back, write-allocate; Outer Write-back, write-allocate; Non-shared]
- 0x0 0
Access permissions 0x3 3 [P:RW U:RW]
- 0x0 0
Execute never 0x0 0
MPU region 6 base 0xFE000000
Base address 0xFE000000 -33554433
MPU region 6 size & enable 0x00000031
Region attributes 0x29 41 [Inner Write-back, write-allocate; Outer Write-back, write-allocate; Non-shared]
- 0x0 0
Access permission 0x3 3 [P:RW U:RW]
- 0x0 0
Execute never 0x0 0
MPU region 7 base 0x00000000
Base address 0x0 0
MPU region 7 size & enable 0x000000000
Enabled 0x0 0
Size 0x0 0 [invalid]
- 0x0 0
Sub-regions disabled 0x0 0 [00000000]
MPU region 7 access control 0x00000000
Region attributes 0x0 0 [Strongly ordered, sharable; ]
- 0x0 0
Access permissions 0x0 0 [P:-- U:--]
- 0x0 0
Execute never 0x0 0
Hi do i have to replace only the cpu CPUI1300.FIR to get ML ? only that's it & format card before ?
thanks a lot
No.
Quote from: Chellyandruu on August 18, 2016, 06:18:12 PM
hey ALEX,on the 80d i got the same information as atonal got on the 7d2.only difference was the first line which read -
CHDK CPU info for 0x350 80d
-----------------------------
ID 0x411FC143.If you need picture proof just tell me.
80D Fw1.02 I have similar data but a few lines more on page1, and page 4
Extra on page 1
Multiprocessor ID 0x00000000
(raw value) 0x0 0
Extra on page 4
SCTRL 0x08E5187D
(raw value) 0x08E5187D 149231741
ACTRL 0x00000030
(raw value) 0x20 32
ACTRL2 0x00000000
(raw value) 0x0 0
CPACR 0x00000000
(raw value) 0x0 0
Page 1
(http://thumb.ibb.co/n8BkDF/80d_fw1_02_PAG1.jpg) (http://ibb.co/n8BkDF)
Page 4
(http://thumb.ibb.co/i0VdYF/80d_fw1_02_PAG4.jpg) (http://ibb.co/i0VdYF)
...and here from the 5Ds, inverted C64 style
(https://thumb.ibb.co/hh72PF/NO8_A8011_corr.jpg) (https://ibb.co/hh72PF) (https://thumb.ibb.co/cSiyya/NO8_A8012_corr.jpg) (https://ibb.co/cSiyya) (https://thumb.ibb.co/jx9tWv/NO8_A8013_corr.jpg) (https://ibb.co/jx9tWv) (https://thumb.ibb.co/dRCQda/NO8_A8014_corr.jpg) (https://ibb.co/dRCQda) (https://thumb.ibb.co/dBYnrv/NO8_A8015_corr.jpg) (https://ibb.co/dBYnrv) (https://thumb.ibb.co/ekiWJa/NO8_A8016_corr.jpg) (https://ibb.co/ekiWJa) (https://thumb.ibb.co/kVR7rv/NO8_A8017_corr.jpg) (https://ibb.co/kVR7rv) (https://thumb.ibb.co/bDUSrv/NO8_A8018_corr.jpg) (https://ibb.co/bDUSrv)
5DS, who would have guessed this
cam being the first D6 cam with bootflag set? Dual D6 ...
Congrats!
Um ... this is not QEMU, right?
yeah its a physical 5Ds with bootflag enabled now :)
basically did a1ex prepare everything needed to do that.
now comes the really hard part - porting!
5Ds + g3gg0 :-*
crossing the fingers. Congrats.
Quote from: g3gg0 on September 03, 2017, 10:55:53 PM
yeah its a physical 5Ds with bootflag enabled now :)
basically did a1ex prepare everything needed to do that.
now comes the really hard part - porting!
Maybe it's too soon but... Can we expect ports to Eos M5, M6, M100?
graphical flash dumper (https://www.youtube.com/watch?v=9mNhph9BfNA) in beta test phase.
you may also call it "3456 parallel led dumper" ;)
(http://ft.trillian.im/c677df06f2ee555dde31c582fce99a2b876ac758/6TeLTz9WvZTlZ4kRkkRkkEsPlmcda.jpg)
Quote from: samuel.cabral on September 04, 2017, 08:41:52 PM
Maybe it's too soon
not just "maybe" - its definitely too soon.
i got hands on a 5Ds and will play now a bit.
this does not imply that there will be a port.
especially as its just given as a loan.
it just means that we can play now a bit
Quote from: samuel.cabral on September 04, 2017, 08:41:52 PM
Maybe it's too soon but... Can we expect ports to Eos M5, M6, M100?
Nope. M5, M100 are running PowerShot code. Devs once mentioned it is more likely to port ML to Nikon ...
Use CHDK instead.
Don't know about M6.
M6 too - https://chdk.setepontos.com/index.php?topic=13210.0
M100? When did that appear? (I thought it's a typo for M10...)
Quote from: a1ex on September 05, 2017, 08:18:36 PM
M6 too - https://chdk.setepontos.com/index.php?topic=13210.0
M100? When did that appear? (I thought it's a typo for M10...)
lol... It's quite new! But it's cheaper (and "weaker") than the m5 and m6!
Hope that we can have raw video in these low budget new cameras.
M100 was annouced last week: https://www.dpreview.com/news/7049088624/canon-launches-eos-m100-with-24mp-sensor-and-dual-pixel-af-for-600
And I confused it with M10,
Updated autoexec.bin from the first post with the latest codebase (https://www.magiclantern.fm/forum/index.php?topic=16534.msg210500#msg210500); it now saves all this info to a file.
Results from 5D3 (same as all other DIGIC 5 models):
CHDK CPU info for 0x285 5D3
------------------------------
ID 0x41059461
Revision 0x1 1
Part 0x946 2374
ARM Arch 0x5 5
Variant 0x0 0
Implementor 0x41 65
Cache type 0x0F192192
Icache words/line 0x2 2 [8]
Icache absent 0x0 0
Icache assoc 0x2 2
Icache size 0x6 6 [32K]
Reserved0_2 0x0 0
Dcache words/line 0x2 2 [8]
Dcache absent 0x0 0
Dcache assoc 0x2 2
Dcache size 0x6 6 [32K]
Reserved1_2 0x0 0
Harvard/unified 0x1 1
Cache type 0x7 7
Reserved2_3 0x0 0
TCM type 0x000C00C0
Reserved0_2 0x0 0
ITCM absent 0x0 0
Reserved1_3 0x0 0
ITCM size 0x3 3 [4K]
Reserved2_4 0x0 0
DTCM absent 0x0 0
Reserved3_2 0x0 0
DTCM size 0x3 3 [4K]
Reserved4_10 0x0 0
Control 0x0005107D
Protect enable 0x1 1
Reserved0_1 0x0 0
Dcache enable 0x1 1
Reserved1_4 0xF 15
Big endian 0x0 0
Reserved2_4 0x0 0
Icache enable 0x1 1
Alt vector 0x0 0
Cache RRR 0x0 0
Disble load TBIT 0x0 0
DTCM enable 0x1 1
DTCM mode 0x0 0
ITCM enable 0x1 1
ITCM mode 0x0 0
Reserved3_12 0x0 0
Protection Region 0 0x0000003F
Enable 0x1 1
Size 0x1F 31 [4G]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 1 0x0000003D
Enable 0x1 1
Size 0x1E 30 [2G]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 2 0xE0000039
Enable 0x1 1
Size 0x1C 28 [512M]
Undef0_7 0x0 0
Base 0x70000 458752 [0xE0000000]
Protection Region 3 0xC0000039
Enable 0x1 1
Size 0x1C 28 [512M]
Undef0_7 0x0 0
Base 0x60000 393216 [0xC0000000]
Protection Region 4 0xFF00002F
Enable 0x1 1
Size 0x17 23 [16M]
Undef0_7 0x0 0
Base 0x7F800 522240 [0xFF000000]
Protection Region 5 0x00000039
Enable 0x1 1
Size 0x1C 28 [512M]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 6 0xF700002F
Enable 0x1 1
Size 0x17 23 [16M]
Undef0_7 0x0 0
Base 0x7B800 505856 [0xF7000000]
Protection Region 7 0x00000000
Enable 0x0 0
Size 0x0 0 [invalid]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Region data perms 0x03333333
Region 0 0x3 3 [P:RW U:RW]
Region 1 0x3 3 [P:RW U:RW]
Region 2 0x3 3 [P:RW U:RW]
Region 3 0x3 3 [P:RW U:RW]
Region 4 0x3 3 [P:RW U:RW]
Region 5 0x3 3 [P:RW U:RW]
Region 6 0x3 3 [P:RW U:RW]
Region 7 0x0 0 [P:-- U:--]
Region inst perms 0x03333333
Region 0 0x3 3 [P:RW U:RW]
Region 1 0x3 3 [P:RW U:RW]
Region 2 0x3 3 [P:RW U:RW]
Region 3 0x3 3 [P:RW U:RW]
Region 4 0x3 3 [P:RW U:RW]
Region 5 0x3 3 [P:RW U:RW]
Region 6 0x3 3 [P:RW U:RW]
Region 7 0x0 0 [P:-- U:--]
DCache cfg 0x00000070
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x0 0
Region 3 0x0 0
Region 4 0x1 1
Region 5 0x1 1
Region 6 0x1 1
Region 7 0x0 0
ICache cfg 0x00000070
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x0 0
Region 3 0x0 0
Region 4 0x1 1
Region 5 0x1 1
Region 6 0x1 1
Region 7 0x0 0
Write buffer 0x00000070
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x0 0
Region 3 0x0 0
Region 4 0x1 1
Region 5 0x1 1
Region 6 0x1 1
Region 7 0x0 0
DTCM cfg 0x40000006
Reserved0_1 0x0 0
Size 0x3 3 [4K]
Undef0_7 0x0 0
Base 0x20000 131072 [0x40000000]
ITCM cfg 0x00000006
Reserved0_1 0x0 0
Size 0x3 3 [4K]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
From 500D (similar to other DIGIC 4, minor differences):
CHDK CPU info for 0x252 500D
------------------------------
ID 0x41059461
Revision 0x1 1
Part 0x946 2374
ARM Arch 0x5 5
Variant 0x0 0
Implementor 0x41 65
Cache type 0x0F112112
Icache words/line 0x2 2 [8]
Icache absent 0x0 0
Icache assoc 0x2 2
Icache size 0x4 4 [8K]
Reserved0_2 0x0 0
Dcache words/line 0x2 2 [8]
Dcache absent 0x0 0
Dcache assoc 0x2 2
Dcache size 0x4 4 [8K]
Reserved1_2 0x0 0
Harvard/unified 0x1 1
Cache type 0x7 7
Reserved2_3 0x0 0
TCM type 0x000C00C0
Reserved0_2 0x0 0
ITCM absent 0x0 0
Reserved1_3 0x0 0
ITCM size 0x3 3 [4K]
Reserved2_4 0x0 0
DTCM absent 0x0 0
Reserved3_2 0x0 0
DTCM size 0x3 3 [4K]
Reserved4_10 0x0 0
Control 0x0005107D
Protect enable 0x1 1
Reserved0_1 0x0 0
Dcache enable 0x1 1
Reserved1_4 0xF 15
Big endian 0x0 0
Reserved2_4 0x0 0
Icache enable 0x1 1
Alt vector 0x0 0
Cache RRR 0x0 0
Disble load TBIT 0x0 0
DTCM enable 0x1 1
DTCM mode 0x0 0
ITCM enable 0x1 1
ITCM mode 0x0 0
Reserved3_12 0x0 0
Protection Region 0 0x0000003F
Enable 0x1 1
Size 0x1F 31 [4G]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 1 0x0000003D
Enable 0x1 1
Size 0x1E 30 [2G]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 2 0xE0000039
Enable 0x1 1
Size 0x1C 28 [512M]
Undef0_7 0x0 0
Base 0x70000 458752 [0xE0000000]
Protection Region 3 0xC0000039
Enable 0x1 1
Size 0x1C 28 [512M]
Undef0_7 0x0 0
Base 0x60000 393216 [0xC0000000]
Protection Region 4 0xFF00002F
Enable 0x1 1
Size 0x17 23 [16M]
Undef0_7 0x0 0
Base 0x7F800 522240 [0xFF000000]
Protection Region 5 0x00000039
Enable 0x1 1
Size 0x1C 28 [512M]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 6 0xF780002D
Enable 0x1 1
Size 0x16 22 [8M]
Undef0_7 0x0 0
Base 0x7BC00 506880 [0xF7800000]
Protection Region 7 0x00000000
Enable 0x0 0
Size 0x0 0 [invalid]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Region data perms 0x03333333
Region 0 0x3 3 [P:RW U:RW]
Region 1 0x3 3 [P:RW U:RW]
Region 2 0x3 3 [P:RW U:RW]
Region 3 0x3 3 [P:RW U:RW]
Region 4 0x3 3 [P:RW U:RW]
Region 5 0x3 3 [P:RW U:RW]
Region 6 0x3 3 [P:RW U:RW]
Region 7 0x0 0 [P:-- U:--]
Region inst perms 0x03333333
Region 0 0x3 3 [P:RW U:RW]
Region 1 0x3 3 [P:RW U:RW]
Region 2 0x3 3 [P:RW U:RW]
Region 3 0x3 3 [P:RW U:RW]
Region 4 0x3 3 [P:RW U:RW]
Region 5 0x3 3 [P:RW U:RW]
Region 6 0x3 3 [P:RW U:RW]
Region 7 0x0 0 [P:-- U:--]
DCache cfg 0x00000070
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x0 0
Region 3 0x0 0
Region 4 0x1 1
Region 5 0x1 1
Region 6 0x1 1
Region 7 0x0 0
ICache cfg 0x00000070
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x0 0
Region 3 0x0 0
Region 4 0x1 1
Region 5 0x1 1
Region 6 0x1 1
Region 7 0x0 0
Write buffer 0x00000070
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x0 0
Region 3 0x0 0
Region 4 0x1 1
Region 5 0x1 1
Region 6 0x1 1
Region 7 0x0 0
DTCM cfg 0x40000006
Reserved0_1 0x0 0
Size 0x3 3 [4K]
Undef0_7 0x0 0
Base 0x20000 131072 [0x40000000]
ITCM cfg 0x00000006
Reserved0_1 0x0 0
Size 0x3 3 [4K]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
From 5D2:
CHDK CPU info for 0x218 5D2
------------------------------
ID 0x41059461
Revision 0x1 1
Part 0x946 2374
ARM Arch 0x5 5
Variant 0x0 0
Implementor 0x41 65
Cache type 0x0F112112
Icache words/line 0x2 2 [8]
Icache absent 0x0 0
Icache assoc 0x2 2
Icache size 0x4 4 [8K]
Reserved0_2 0x0 0
Dcache words/line 0x2 2 [8]
Dcache absent 0x0 0
Dcache assoc 0x2 2
Dcache size 0x4 4 [8K]
Reserved1_2 0x0 0
Harvard/unified 0x1 1
Cache type 0x7 7
Reserved2_3 0x0 0
TCM type 0x000C00C0
Reserved0_2 0x0 0
ITCM absent 0x0 0
Reserved1_3 0x0 0
ITCM size 0x3 3 [4K]
Reserved2_4 0x0 0
DTCM absent 0x0 0
Reserved3_2 0x0 0
DTCM size 0x3 3 [4K]
Reserved4_10 0x0 0
Control 0x0005107D
Protect enable 0x1 1
Reserved0_1 0x0 0
Dcache enable 0x1 1
Reserved1_4 0xF 15
Big endian 0x0 0
Reserved2_4 0x0 0
Icache enable 0x1 1
Alt vector 0x0 0
Cache RRR 0x0 0
Disble load TBIT 0x0 0
DTCM enable 0x1 1
DTCM mode 0x0 0
ITCM enable 0x1 1
ITCM mode 0x0 0
Reserved3_12 0x0 0
Protection Region 0 0x0000003F
Enable 0x1 1
Size 0x1F 31 [4G]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 1 0x0000003D
Enable 0x1 1
Size 0x1E 30 [2G]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 2 0xE0000039
Enable 0x1 1
Size 0x1C 28 [512M]
Undef0_7 0x0 0
Base 0x70000 458752 [0xE0000000]
Protection Region 3 0xC0000039
Enable 0x1 1
Size 0x1C 28 [512M]
Undef0_7 0x0 0
Base 0x60000 393216 [0xC0000000]
Protection Region 4 0xFF80002D
Enable 0x1 1
Size 0x16 22 [8M]
Undef0_7 0x0 0
Base 0x7FC00 523264 [0xFF800000]
Protection Region 5 0x00000039
Enable 0x1 1
Size 0x1C 28 [512M]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 6 0xF780002D
Enable 0x1 1
Size 0x16 22 [8M]
Undef0_7 0x0 0
Base 0x7BC00 506880 [0xF7800000]
Protection Region 7 0x00000000
Enable 0x0 0
Size 0x0 0 [invalid]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Region data perms 0x03333333
Region 0 0x3 3 [P:RW U:RW]
Region 1 0x3 3 [P:RW U:RW]
Region 2 0x3 3 [P:RW U:RW]
Region 3 0x3 3 [P:RW U:RW]
Region 4 0x3 3 [P:RW U:RW]
Region 5 0x3 3 [P:RW U:RW]
Region 6 0x3 3 [P:RW U:RW]
Region 7 0x0 0 [P:-- U:--]
Region inst perms 0x03333333
Region 0 0x3 3 [P:RW U:RW]
Region 1 0x3 3 [P:RW U:RW]
Region 2 0x3 3 [P:RW U:RW]
Region 3 0x3 3 [P:RW U:RW]
Region 4 0x3 3 [P:RW U:RW]
Region 5 0x3 3 [P:RW U:RW]
Region 6 0x3 3 [P:RW U:RW]
Region 7 0x0 0 [P:-- U:--]
DCache cfg 0x00000070
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x0 0
Region 3 0x0 0
Region 4 0x1 1
Region 5 0x1 1
Region 6 0x1 1
Region 7 0x0 0
ICache cfg 0x00000070
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x0 0
Region 3 0x0 0
Region 4 0x1 1
Region 5 0x1 1
Region 6 0x1 1
Region 7 0x0 0
Write buffer 0x00000070
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x0 0
Region 3 0x0 0
Region 4 0x1 1
Region 5 0x1 1
Region 6 0x1 1
Region 7 0x0 0
DTCM cfg 0x40000006
Reserved0_1 0x0 0
Size 0x3 3 [4K]
Undef0_7 0x0 0
Base 0x20000 131072 [0x40000000]
ITCM cfg 0x00000006
Reserved0_1 0x0 0
Size 0x3 3 [4K]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
From 7D:
CHDK CPU info for 0x250 7D
------------------------------
ID 0x41059461
Revision 0x1 1
Part 0x946 2374
ARM Arch 0x5 5
Variant 0x0 0
Implementor 0x41 65
Cache type 0x0F112112
Icache words/line 0x2 2 [8]
Icache absent 0x0 0
Icache assoc 0x2 2
Icache size 0x4 4 [8K]
Reserved0_2 0x0 0
Dcache words/line 0x2 2 [8]
Dcache absent 0x0 0
Dcache assoc 0x2 2
Dcache size 0x4 4 [8K]
Reserved1_2 0x0 0
Harvard/unified 0x1 1
Cache type 0x7 7
Reserved2_3 0x0 0
TCM type 0x000C00C0
Reserved0_2 0x0 0
ITCM absent 0x0 0
Reserved1_3 0x0 0
ITCM size 0x3 3 [4K]
Reserved2_4 0x0 0
DTCM absent 0x0 0
Reserved3_2 0x0 0
DTCM size 0x3 3 [4K]
Reserved4_10 0x0 0
Control 0x0005107D
Protect enable 0x1 1
Reserved0_1 0x0 0
Dcache enable 0x1 1
Reserved1_4 0xF 15
Big endian 0x0 0
Reserved2_4 0x0 0
Icache enable 0x1 1
Alt vector 0x0 0
Cache RRR 0x0 0
Disble load TBIT 0x0 0
DTCM enable 0x1 1
DTCM mode 0x0 0
ITCM enable 0x1 1
ITCM mode 0x0 0
Reserved3_12 0x0 0
Protection Region 0 0x0000003F
Enable 0x1 1
Size 0x1F 31 [4G]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 1 0x0000003D
Enable 0x1 1
Size 0x1E 30 [2G]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 2 0xE0000039
Enable 0x1 1
Size 0x1C 28 [512M]
Undef0_7 0x0 0
Base 0x70000 458752 [0xE0000000]
Protection Region 3 0xC0000039
Enable 0x1 1
Size 0x1C 28 [512M]
Undef0_7 0x0 0
Base 0x60000 393216 [0xC0000000]
Protection Region 4 0xFF80002F
Enable 0x1 1
Size 0x17 23 [16M]
Undef0_7 0x0 0
Base 0x7FC00 523264 [0xFF800000]
Protection Region 5 0x00000039
Enable 0x1 1
Size 0x1C 28 [512M]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 6 0x8000002F
Enable 0x1 1
Size 0x17 23 [16M]
Undef0_7 0x0 0
Base 0x40000 262144 [0x80000000]
Protection Region 7 0x00000000
Enable 0x0 0
Size 0x0 0 [invalid]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Region data perms 0x03333333
Region 0 0x3 3 [P:RW U:RW]
Region 1 0x3 3 [P:RW U:RW]
Region 2 0x3 3 [P:RW U:RW]
Region 3 0x3 3 [P:RW U:RW]
Region 4 0x3 3 [P:RW U:RW]
Region 5 0x3 3 [P:RW U:RW]
Region 6 0x3 3 [P:RW U:RW]
Region 7 0x0 0 [P:-- U:--]
Region inst perms 0x03333333
Region 0 0x3 3 [P:RW U:RW]
Region 1 0x3 3 [P:RW U:RW]
Region 2 0x3 3 [P:RW U:RW]
Region 3 0x3 3 [P:RW U:RW]
Region 4 0x3 3 [P:RW U:RW]
Region 5 0x3 3 [P:RW U:RW]
Region 6 0x3 3 [P:RW U:RW]
Region 7 0x0 0 [P:-- U:--]
DCache cfg 0x00000030
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x0 0
Region 3 0x0 0
Region 4 0x1 1
Region 5 0x1 1
Region 6 0x0 0
Region 7 0x0 0
ICache cfg 0x00000030
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x0 0
Region 3 0x0 0
Region 4 0x1 1
Region 5 0x1 1
Region 6 0x0 0
Region 7 0x0 0
Write buffer 0x00000030
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x0 0
Region 3 0x0 0
Region 4 0x1 1
Region 5 0x1 1
Region 6 0x0 0
Region 7 0x0 0
DTCM cfg 0x40000006
Reserved0_1 0x0 0
Size 0x3 3 [4K]
Undef0_7 0x0 0
Base 0x20000 131072 [0x40000000]
ITCM cfg 0x00000006
Reserved0_1 0x0 0
Size 0x3 3 [4K]
Undef0_7 0x0 0
Base 0
From 200D:
CHDK CPU info for 0x417 200D
------------------------------
ID 0x414FC091
Revision 0x1 1
Part 0xC09 3081
ARM Arch 0xF 15
Variant 0x4 4
Implementor 0x41 65
Cache type 0x83338003
Icache min words/line 0x3 3 [8]
(zero) 0x0 0
L1 Icache policy 0x2 2
Dcache min words/line 0x3 3 [8]
Exclusives Reservation Granule 0x3 3 [8]
Cache Writeback Granule 0x3 3 [8]
(zero) 0x0 0
(register format) 0x4 4
TCM type 0x00000000
(raw value) 0x0 0
MPU type 0x414FC091
S 0x1 1
- 0x48 72
Num of MPU regions 0xC0 192
Multiprocessor ID 0x80000000
(raw value) 0x80000000 -2147483648
Processor feature 0 0x00001231
ARM inst set 0x1 1
Thumb inst set 0x3 3
Jazelle inst set 0x2 2
ThumbEE inst set 0x1 1
- 0x0 0
Processor feature 1 0x00000011
Programmers' model 0x1 1
Security extensions 0x1 1
Microcontr. prog model 0x0 0
- 0x0 0
Debug feature 0x00010444
(raw value) 0x10444 66628
Aux feature 0x00000000
(raw value) 0x0 0
Mem model feature 0 0x00100103
VMSA support 0x3 3
PMSA support 0x0 0
Cache coherence 0x1 1
Outer shareable 0x0 0
TCM support 0x0 0
Auxiliary registers 0x1 1
FCSE support 0x0 0
- 0x0 0
Mem model feature 1 0x20000000
L1 Harvard cache VA 0x0 0
L1 unified cache VA 0x0 0
L1 Harvard cache s/w 0x0 0
L1 unified cache s/w 0x0 0
L1 Harvard cache 0x0 0
L1 unified cache 0x0 0
L1 cache test & clean 0x0 0
Branch predictor 0x2 2
Mem model feature 2 0x01230000
L1 Harvard fg prefetch 0x0 0
L1 Harvard bg prefetch 0x0 0
L1 Harvard range 0x0 0
Harvard TLB 0x0 0
Unified TLB 0x3 3
Mem barrier 0x2 2
WFI stall 0x1 1
HW access flag 0x0 0
Mem model feature 3 0x00102111
Cache maintain MVA 0x1 1
Cache maintain s/w 0x1 1
BP maintain 0x1 1
- 0x102 258
Supersection support 0x0 0
ISA feature 0 0x00101111
Swap instrs 0x1 1
Bitcount instrs 0x1 1
Bitfield instrs 0x1 1
CmpBranch instrs 0x1 1
Coproc instrs 0x0 0
Debug instrs 0x1 1
Divide instrs 0x0 0
- 0x0 0
ISA feature 1 0x13112111
Endian instrs 0x1 1
Exception instrs 0x1 1
Exception AR instrs 0x1 1
Extend instrs 0x2 2
IfThen instrs 0x1 1
Immediate instrs 0x1 1
Interwork instrs 0x3 3
Jazelle instrs 0x1 1
ISA feature 2 0x21232041
LoadStore instrs 0x1 1
Memhint instrs 0x4 4
MultiAccess Interruptible instructions 0x0 0
Mult instrs 0x2 2
MultS instrs 0x3 3
MultU instrs 0x2 2
PSR AR instrs 0x1 1
Reversal instrs 0x2 2
ISA feature 3 0x11112131
Saturate instrs 0x1 1
SIMD instrs 0x3 3
SVC instrs 0x1 1
SynchPrim instrs 0x2 2
TabBranch instrs 0x1 1
ThumbCopy instrs 0x1 1
TrueNOP instrs 0x1 1
T2 Exec Env instrs 0x1 1
ISA feature 4 0x00011142
Unprivileged instrs 0x2 2
WithShifts instrs 0x4 4
Writeback instrs 0x1 1
SMC instrs 0x1 1
Barrier instrs 0x1 1
SynchPrim_instrs_frac 0x0 0
PSR_M instrs 0x0 0
- 0x0 0
ISA feature 5 0x00000000
- 0x0 0
Cache level ID 0x09200003
Cache type, level1 0x3 3 [Separate Icache, Dcache]
Cache type, level2 0x0 0 [no cache]
Cache type, level3 0x0 0 [no cache]
Cache type, level4 0x0 0 [no cache]
Cache type, level5 0x0 0 [no cache]
Cache type, level6 0x0 0 [no cache]
Cache type, level7 0x0 0 [no cache]
Cache type, level8 0x1 1 [Icache only]
Level of coherency 0x1 1
Level of unification 0x1 1
(zero) 0x0 0
Cache size ID reg (data, level0) 0x700FE019
Line size in words 0x1 1 [8]
Associativity 0x3 3 [4]
Number of sets 0x7F 127 [128]
Write allocation 0x1 1
Read allocation 0x1 1
Write back 0x1 1
Write through 0x0 0
Cache size ID reg (inst, level0) 0x200FE019
Line size in words 0x1 1 [8]
Associativity 0x3 3 [4]
Number of sets 0x7F 127 [128]
Write allocation 0x0 0
Read allocation 0x1 1
Write back 0x0 0
Write through 0x0 0
SCTLR 0x48C5187D
MPU Enable 0x1 1
Strict Align 0x0 0
L1 DCache Enable 0x1 1
- (SBO) 0xF 15
- (SBZ) 0x0 0
Branch Pred Enable 0x1 1
L1 ICache Enable 0x1 1
High Vectors 0x0 0
Round Robin 0x0 0
- (SBZ) 0x0 0
- (SBO) 0x1 1
MPU background reg 0x0 0
- (SBO) 0x1 1
Div0 exception 0x0 0
- (SBZ) 0x0 0
FIQ Enable 0x0 0
- (SBO) 0x3 3
VIC 0x0 0
CPSR E bit 0x0 0
- (SBZ) 0x0 0
NMFI 0x1 1
TRE 0x0 0
AFE 0x0 0
Thumb exceptions 0x1 1
Big endian 0x0 0
ACTLR 0x00000045
(raw value) 0x45 69
ACTLR2 0x00000201
(raw value) 0x201 513
CPACR 0xC0000000
(raw value) 0xC0000000 -1073741824
DBGDIDR 0x35137041
Revision 0x1 1
Variant 0x4 4
- (RAZ) 0x70 112
Version 0x3 3 [v7 full]
Context 0x1 1 [2]
BRP 0x5 5 [6]
WRP 0x3 3 [4]
DBGDRAR 0x00000000
Valid 0x0 0
- (UNK) 0x0 0
Address 0x0 0 [0x00000000]
DBGDSAR 0x00030000
Valid 0x0 0
- (UNK) 0x0 0
Address 0x30 48 [0x00030000]
DBGDSCR 0x03000002
HALTED 0x0 0
RESTARTED 0x1 1
MOE 0x0 0
SDABORT_l 0x0 0
ADABORT_l 0x0 0
UND_l 0x0 0
FS 0x0 0
DBGack 0x0 0
INTdis 0x0 0
UDCCdis 0x0 0
ITRen 0x0 0
HDBGen 0x0 0
MDBGen 0x0 0
SPIDdis 0x0 0
SPNIDdis 0x0 0
NS 0x0 0
ADAdiscard 0x0 0
ExtDCCmode 0x0 0
- (SBZ) 0x0 0
InstrCompl_l 0x1 1
PipeAdv 0x1 1
TXfull_l 0x0 0
RXfull_l 0x0 0
- (SBZ) 0x0 0
TXfull 0x0 0
RXfull 0x0 0
- (SBZ) 0x0 0
From M50 / SX70:
CHDK CPU info for 0x412 M50 / 0x805 SX70
------------------------------
ID 0x414FC091
Revision 0x1 1
Part 0xC09 3081
ARM Arch 0xF 15
Variant 0x4 4
Implementor 0x41 65
Cache type 0x83338003
Icache min words/line 0x3 3 [8]
(zero) 0x0 0
L1 Icache policy 0x2 2
Dcache min words/line 0x3 3 [8]
Exclusives Reservation Granule 0x3 3 [8]
Cache Writeback Granule 0x3 3 [8]
(zero) 0x0 0
(register format) 0x4 4
TCM type 0x00000000
(raw value) 0x0 0
MPU type 0x414FC091
S 0x1 1
- 0x48 72
Num of MPU regions 0xC0 192
Multiprocessor ID 0x80000000
(raw value) 0x80000000 -2147483648
Processor feature 0 0x00001231
ARM inst set 0x1 1
Thumb inst set 0x3 3
Jazelle inst set 0x2 2
ThumbEE inst set 0x1 1
- 0x0 0
Processor feature 1 0x00000011
Programmers' model 0x1 1
Security extensions 0x1 1
Microcontr. prog model 0x0 0
- 0x0 0
Debug feature 0x00010444
(raw value) 0x10444 66628
Aux feature 0x00000000
(raw value) 0x0 0
Mem model feature 0 0x00100103
VMSA support 0x3 3
PMSA support 0x0 0
Cache coherence 0x1 1
Outer shareable 0x0 0
TCM support 0x0 0
Auxiliary registers 0x1 1
FCSE support 0x0 0
- 0x0 0
Mem model feature 1 0x20000000
L1 Harvard cache VA 0x0 0
L1 unified cache VA 0x0 0
L1 Harvard cache s/w 0x0 0
L1 unified cache s/w 0x0 0
L1 Harvard cache 0x0 0
L1 unified cache 0x0 0
L1 cache test & clean 0x0 0
Branch predictor 0x2 2
Mem model feature 2 0x01230000
L1 Harvard fg prefetch 0x0 0
L1 Harvard bg prefetch 0x0 0
L1 Harvard range 0x0 0
Harvard TLB 0x0 0
Unified TLB 0x3 3
Mem barrier 0x2 2
WFI stall 0x1 1
HW access flag 0x0 0
Mem model feature 3 0x00102111
Cache maintain MVA 0x1 1
Cache maintain s/w 0x1 1
BP maintain 0x1 1
- 0x102 258
Supersection support 0x0 0
ISA feature 0 0x00101111
Swap instrs 0x1 1
Bitcount instrs 0x1 1
Bitfield instrs 0x1 1
CmpBranch instrs 0x1 1
Coproc instrs 0x0 0
Debug instrs 0x1 1
Divide instrs 0x0 0
- 0x0 0
ISA feature 1 0x13112111
Endian instrs 0x1 1
Exception instrs 0x1 1
Exception AR instrs 0x1 1
Extend instrs 0x2 2
IfThen instrs 0x1 1
Immediate instrs 0x1 1
Interwork instrs 0x3 3
Jazelle instrs 0x1 1
ISA feature 2 0x21232041
LoadStore instrs 0x1 1
Memhint instrs 0x4 4
MultiAccess Interruptible instructions 0x0 0
Mult instrs 0x2 2
MultS instrs 0x3 3
MultU instrs 0x2 2
PSR AR instrs 0x1 1
Reversal instrs 0x2 2
ISA feature 3 0x11112131
Saturate instrs 0x1 1
SIMD instrs 0x3 3
SVC instrs 0x1 1
SynchPrim instrs 0x2 2
TabBranch instrs 0x1 1
ThumbCopy instrs 0x1 1
TrueNOP instrs 0x1 1
T2 Exec Env instrs 0x1 1
ISA feature 4 0x00011142
Unprivileged instrs 0x2 2
WithShifts instrs 0x4 4
Writeback instrs 0x1 1
SMC instrs 0x1 1
Barrier instrs 0x1 1
SynchPrim_instrs_frac 0x0 0
PSR_M instrs 0x0 0
- 0x0 0
ISA feature 5 0x00000000
- 0x0 0
Cache level ID 0x09200003
Cache type, level1 0x3 3 [Separate Icache, Dcache]
Cache type, level2 0x0 0 [no cache]
Cache type, level3 0x0 0 [no cache]
Cache type, level4 0x0 0 [no cache]
Cache type, level5 0x0 0 [no cache]
Cache type, level6 0x0 0 [no cache]
Cache type, level7 0x0 0 [no cache]
Cache type, level8 0x1 1 [Icache only]
Level of coherency 0x1 1
Level of unification 0x1 1
(zero) 0x0 0
Cache size ID reg (data, level0) 0x700FE019
Line size in words 0x1 1 [8]
Associativity 0x3 3 [4]
Number of sets 0x7F 127 [128]
Write allocation 0x1 1
Read allocation 0x1 1
Write back 0x1 1
Write through 0x0 0
Cache size ID reg (inst, level0) 0x200FE019
Line size in words 0x1 1 [8]
Associativity 0x3 3 [4]
Number of sets 0x7F 127 [128]
Write allocation 0x0 0
Read allocation 0x1 1
Write back 0x0 0
Write through 0x0 0
SCTLR 0x40C5187D
MPU Enable 0x1 1
Strict Align 0x0 0
L1 DCache Enable 0x1 1
- (SBO) 0xF 15
- (SBZ) 0x0 0
Branch Pred Enable 0x1 1
L1 ICache Enable 0x1 1
High Vectors 0x0 0
Round Robin 0x0 0
- (SBZ) 0x0 0
- (SBO) 0x1 1
MPU background reg 0x0 0
- (SBO) 0x1 1
Div0 exception 0x0 0
- (SBZ) 0x0 0
FIQ Enable 0x0 0
- (SBO) 0x3 3
VIC 0x0 0
CPSR E bit 0x0 0
- (SBZ) 0x0 0
NMFI 0x0 0
TRE 0x0 0
AFE 0x0 0
Thumb exceptions 0x1 1
Big endian 0x0 0
ACTLR 0x00000045
(raw value) 0x45 69
ACTLR2 0x00000701
(raw value) 0x701 1793
CPACR 0xC0000000
(raw value) 0xC0000000 -1073741824
DBGDIDR 0x35137041
Revision 0x1 1
Variant 0x4 4
- (RAZ) 0x70 112
Version 0x3 3 [v7 full]
Context 0x1 1 [2]
BRP 0x5 5 [6]
WRP 0x3 3 [4]
DBGDRAR 0x00000000
Valid 0x0 0
- (UNK) 0x0 0
Address 0x0 0 [0x00000000]
DBGDSAR 0x00030000
Valid 0x0 0
- (UNK) 0x0 0
Address 0x30 48 [0x00030000]
DBGDSCR 0x03000002
HALTED 0x0 0
RESTARTED 0x1 1
MOE 0x0 0
SDABORT_l 0x0 0
ADABORT_l 0x0 0
UND_l 0x0 0
FS 0x0 0
DBGack 0x0 0
INTdis 0x0 0
UDCCdis 0x0 0
ITRen 0x0 0
HDBGen 0x0 0
MDBGen 0x0 0
SPIDdis 0x0 0
SPNIDdis 0x0 0
NS 0x0 0
ADAdiscard 0x0 0
ExtDCCmode 0x0 0
- (SBZ) 0x0 0
InstrCompl_l 0x1 1
PipeAdv 0x1 1
TXfull_l 0x0 0
RXfull_l 0x0 0
- (SBZ) 0x0 0
TXfull 0x0 0
RXfull 0x0 0
- (SBZ) 0x0 0
Most of the info from the logs in this thread was integrated in the emulator (https://www.magiclantern.fm/forum/index.php?topic=2864.msg209934#msg209934). If you run the autoexec.bin from this post in QEMU, you should get very similar logs. There will be a few minor differences, but fixing them is more difficult than "just" declaring some constants.
FIR files (built from 2a15b7d (https://bitbucket.org/hudson/magic-lantern/branch/recovery) with CONFIG_BOOT_FULLFAT=y CONFIG_BOOT_CPUINFO=y):
DIGIC 4+: 1300D (https://a1ex.magiclantern.fm/debug/portable-cpuinfo/CPU1300D.FIR) 2000D (https://a1ex.magiclantern.fm/debug/portable-cpuinfo/CPU2000D.FIR) 4000D (https://a1ex.magiclantern.fm/debug/portable-cpuinfo/CPU4000D.FIR)
DIGIC 6: 5D4 (https://a1ex.magiclantern.fm/debug/portable-cpuinfo/CPUI_5D4.FIR) 750D (https://a1ex.magiclantern.fm/debug/portable-cpuinfo/CPUI750D.FIR) 760D (https://a1ex.magiclantern.fm/debug/portable-cpuinfo/CPUI760D.FIR) 80D (https://a1ex.magiclantern.fm/debug/portable-cpuinfo/CPUI_80D.FIR)
DIGIC 7: 200D (https://a1ex.magiclantern.fm/debug/portable-cpuinfo/CPUI200D.FIR) 6D2 (https://a1ex.magiclantern.fm/debug/portable-cpuinfo/CPUI_6D2.FIR) 77D (https://a1ex.magiclantern.fm/debug/portable-cpuinfo/CPUI_77D.FIR) 800D (https://a1ex.magiclantern.fm/debug/portable-cpuinfo/CPUI800D.FIR)
DIGIC 8: EOSR (https://a1ex.magiclantern.fm/debug/portable-cpuinfo/CPUIEOSR.FIR) M50 (https://a1ex.magiclantern.fm/debug/portable-cpuinfo/CPUI_M50.FIR) SX70 (https://a1ex.magiclantern.fm/debug/portable-cpuinfo/CPUISX70.FIR) SX740 (https://a1ex.magiclantern.fm/debug/portable-cpuinfo/CPUSX740.FIR)
Master/Slave: 5DS (https://a1ex.magiclantern.fm/debug/portable-cpuinfo/CPUI_5DS.FIR) 5DSR (https://a1ex.magiclantern.fm/debug/portable-cpuinfo/CPUI5DSR.FIR) 7D (https://a1ex.magiclantern.fm/debug/portable-cpuinfo/CPUI__7D.FIR) 7D2 (https://a1ex.magiclantern.fm/debug/portable-cpuinfo/CPUI_7D2.FIR)
Oldies: 1000D (https://a1ex.magiclantern.fm/debug/portable-cpuinfo/CPU1000D.FIR) 30D (https://a1ex.magiclantern.fm/debug/portable-cpuinfo/CPUI_30D.FIR) 400D (https://a1ex.magiclantern.fm/debug/portable-cpuinfo/CPUI400D.FIR) 40D (https://a1ex.magiclantern.fm/debug/portable-cpuinfo/CPUI_40D.FIR) 450D (https://a1ex.magiclantern.fm/debug/portable-cpuinfo/CPUI450D.FIR) 5D (https://a1ex.magiclantern.fm/debug/portable-cpuinfo/CPUI__5D.FIR)
Feel free to re-submit logs, even if some were covered in previous posts. The last version saves this info as plain text, rather than just printing it on the screen.
600D
CHDK CPU info for 0x286 600D
------------------------------
ID 0x41059461
Revision 0x1 1
Part 0x946 2374
ARM Arch 0x5 5
Variant 0x0 0
Implementor 0x41 65
Cache type 0x0F112112
Icache words/line 0x2 2 [8]
Icache absent 0x0 0
Icache assoc 0x2 2
Icache size 0x4 4 [8K]
Reserved0_2 0x0 0
Dcache words/line 0x2 2 [8]
Dcache absent 0x0 0
Dcache assoc 0x2 2
Dcache size 0x4 4 [8K]
Reserved1_2 0x0 0
Harvard/unified 0x1 1
Cache type 0x7 7
Reserved2_3 0x0 0
TCM type 0x000C00C0
Reserved0_2 0x0 0
ITCM absent 0x0 0
Reserved1_3 0x0 0
ITCM size 0x3 3 [4K]
Reserved2_4 0x0 0
DTCM absent 0x0 0
Reserved3_2 0x0 0
DTCM size 0x3 3 [4K]
Reserved4_10 0x0 0
Control 0x0005107D
Protect enable 0x1 1
Reserved0_1 0x0 0
Dcache enable 0x1 1
Reserved1_4 0xF 15
Big endian 0x0 0
Reserved2_4 0x0 0
Icache enable 0x1 1
Alt vector 0x0 0
Cache RRR 0x0 0
Disble load TBIT 0x0 0
DTCM enable 0x1 1
DTCM mode 0x0 0
ITCM enable 0x1 1
ITCM mode 0x0 0
Reserved3_12 0x0 0
Protection Region 0 0x0000003F
Enable 0x1 1
Size 0x1F 31 [4G]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 1 0x0000003D
Enable 0x1 1
Size 0x1E 30 [2G]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 2 0xE0000039
Enable 0x1 1
Size 0x1C 28 [512M]
Undef0_7 0x0 0
Base 0x70000 458752 [0xE0000000]
Protection Region 3 0xC0000039
Enable 0x1 1
Size 0x1C 28 [512M]
Undef0_7 0x0 0
Base 0x60000 393216 [0xC0000000]
Protection Region 4 0xFF00002F
Enable 0x1 1
Size 0x17 23 [16M]
Undef0_7 0x0 0
Base 0x7F800 522240 [0xFF000000]
Protection Region 5 0x00000037
Enable 0x1 1
Size 0x1B 27 [256M]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 6 0xF780002D
Enable 0x1 1
Size 0x16 22 [8M]
Undef0_7 0x0 0
Base 0x7BC00 506880 [0xF7800000]
Protection Region 7 0x00000000
Enable 0x0 0
Size 0x0 0 [invalid]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Region data perms 0x03333333
Region 0 0x3 3 [P:RW U:RW]
Region 1 0x3 3 [P:RW U:RW]
Region 2 0x3 3 [P:RW U:RW]
Region 3 0x3 3 [P:RW U:RW]
Region 4 0x3 3 [P:RW U:RW]
Region 5 0x3 3 [P:RW U:RW]
Region 6 0x3 3 [P:RW U:RW]
Region 7 0x0 0 [P:-- U:--]
Region inst perms 0x03333333
Region 0 0x3 3 [P:RW U:RW]
Region 1 0x3 3 [P:RW U:RW]
Region 2 0x3 3 [P:RW U:RW]
Region 3 0x3 3 [P:RW U:RW]
Region 4 0x3 3 [P:RW U:RW]
Region 5 0x3 3 [P:RW U:RW]
Region 6 0x3 3 [P:RW U:RW]
Region 7 0x0 0 [P:-- U:--]
DCache cfg 0x00000070
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x0 0
Region 3 0x0 0
Region 4 0x1 1
Region 5 0x1 1
Region 6 0x1 1
Region 7 0x0 0
ICache cfg 0x00000070
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x0 0
Region 3 0x0 0
Region 4 0x1 1
Region 5 0x1 1
Region 6 0x1 1
Region 7 0x0 0
Write buffer 0x00000070
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x0 0
Region 3 0x0 0
Region 4 0x1 1
Region 5 0x1 1
Region 6 0x1 1
Region 7 0x0 0
DTCM cfg 0x40000006
Reserved0_1 0x0 0
Size 0x3 3 [4K]
Undef0_7 0x0 0
Base 0x20000 131072 [0x40000000]
ITCM cfg 0x00000006
Reserved0_1 0x0 0
Size 0x3 3 [4K]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
1300D
Magic Lantern Rescue
----------------------------
- Model ID: 0x404 1300D
- Camera model: Canon EOS Rebel T6 / Kiss X80
- Firmware version: 1.1.0 / 4.4.7 37(0b)
- IMG naming: 100CANON/IMG_9540.JPG
- Boot flags: FIR=0 BOOT=0 RAM=-1 UPD=-1
- ROMBASEADDR: 0xFE0C0000
CHDK CPU info for 0x404 1300D
------------------------------
ID 0x41059461
Revision 0x1 1
Part 0x946 2374
ARM Arch 0x5 5
Variant 0x0 0
Implementor 0x41 65
Cache type 0x0F112112
Icache words/line 0x2 2 [8]
Icache absent 0x0 0
Icache assoc 0x2 2
Icache size 0x4 4 [8K]
Reserved0_2 0x0 0
Dcache words/line 0x2 2 [8]
Dcache absent 0x0 0
Dcache assoc 0x2 2
Dcache size 0x4 4 [8K]
Reserved1_2 0x0 0
Harvard/unified 0x1 1
Cache type 0x7 7
Reserved2_3 0x0 0
TCM type 0x000C00C0
Reserved0_2 0x0 0
ITCM absent 0x0 0
Reserved1_3 0x0 0
ITCM size 0x3 3 [4K]
Reserved2_4 0x0 0
DTCM absent 0x0 0
Reserved3_2 0x0 0
DTCM size 0x3 3 [4K]
Reserved4_10 0x0 0
Control 0x0005107D
Protect enable 0x1 1
Reserved0_1 0x0 0
Dcache enable 0x1 1
Reserved1_4 0xF 15
Big endian 0x0 0
Reserved2_4 0x0 0
Icache enable 0x1 1
Alt vector 0x0 0
Cache RRR 0x0 0
Disble load TBIT 0x0 0
DTCM enable 0x1 1
DTCM mode 0x0 0
ITCM enable 0x1 1
ITCM mode 0x0 0
Reserved3_12 0x0 0
Protection Region 0 0x0000003F
Enable 0x1 1
Size 0x1F 31 [4G]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 1 0x0000003D
Enable 0x1 1
Size 0x1E 30 [2G]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 2 0x00000037
Enable 0x1 1
Size 0x1B 27 [256M]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 3 0xC0000039
Enable 0x1 1
Size 0x1C 28 [512M]
Undef0_7 0x0 0
Base 0x60000 393216 [0xC0000000]
Protection Region 4 0xF8000031
Enable 0x1 1
Size 0x18 24 [32M]
Undef0_7 0x0 0
Base 0x7C000 507904 [0xF8000000]
Protection Region 5 0xFE000031
Enable 0x1 1
Size 0x18 24 [32M]
Undef0_7 0x0 0
Base 0x7F000 520192 [0xFE000000]
Protection Region 6 0x00000000
Enable 0x0 0
Size 0x0 0 [invalid]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 7 0x00000000
Enable 0x0 0
Size 0x0 0 [invalid]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Region data perms 0x00333333
Region 0 0x3 3 [P:RW U:RW]
Region 1 0x3 3 [P:RW U:RW]
Region 2 0x3 3 [P:RW U:RW]
Region 3 0x3 3 [P:RW U:RW]
Region 4 0x3 3 [P:RW U:RW]
Region 5 0x3 3 [P:RW U:RW]
Region 6 0x0 0 [P:-- U:--]
Region 7 0x0 0 [P:-- U:--]
Region inst perms 0x00333333
Region 0 0x3 3 [P:RW U:RW]
Region 1 0x3 3 [P:RW U:RW]
Region 2 0x3 3 [P:RW U:RW]
Region 3 0x3 3 [P:RW U:RW]
Region 4 0x3 3 [P:RW U:RW]
Region 5 0x3 3 [P:RW U:RW]
Region 6 0x0 0 [P:-- U:--]
Region 7 0x0 0 [P:-- U:--]
DCache cfg 0x00000024
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x1 1
Region 3 0x0 0
Region 4 0x0 0
Region 5 0x1 1
Region 6 0x0 0
Region 7 0x0 0
ICache cfg 0x00000024
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x1 1
Region 3 0x0 0
Region 4 0x0 0
Region 5 0x1 1
Region 6 0x0 0
Region 7 0x0 0
Write buffer 0x00000024
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x1 1
Region 3 0x0 0
Region 4 0x0 0
Region 5 0x1 1
Region 6 0x0 0
Region 7 0x0 0
DTCM cfg 0x40000006
Reserved0_1 0x0 0
Size 0x3 3 [4K]
Undef0_7 0x0 0
Base 0x20000 131072 [0x40000000]
ITCM cfg 0x00000006
Reserved0_1 0x0 0
Size 0x3 3 [4K]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
- card_bootflags 1069cc
- boot_read/write_sector 1071c0 1072b8
- 101F64 Card init => 2
- Saving RESCUE.LOG ...
Canon 40D
Magic Lantern Rescue
----------------------------
- Model ID: 0x190 40D
- Camera model: Canon EOS 40D
- Firmware version: 1.1.1 / 4.0.1 6C(3e)
- IMG naming: 100CANON/IMG_9371.JPG
- Boot flags: FIR=0 BOOT=-1 RAM=-1 UPD=-1
- ROMBASEADDR: 0xFF810000
CHDK CPU info for 0x190 40D
------------------------------
ID 0x41059461
Revision 0x1 1
Part 0x946 2374
ARM Arch 0x5 5
Variant 0x0 0
Implementor 0x41 65
Cache type 0x0F112112
Icache words/line 0x2 2 [8]
Icache absent 0x0 0
Icache assoc 0x2 2
Icache size 0x4 4 [8K]
Reserved0_2 0x0 0
Dcache words/line 0x2 2 [8]
Dcache absent 0x0 0
Dcache assoc 0x2 2
Dcache size 0x4 4 [8K]
Reserved1_2 0x0 0
Harvard/unified 0x1 1
Cache type 0x7 7
Reserved2_3 0x0 0
TCM type 0x000C00C0
Reserved0_2 0x0 0
ITCM absent 0x0 0
Reserved1_3 0x0 0
ITCM size 0x3 3 [4K]
Reserved2_4 0x0 0
DTCM absent 0x0 0
Reserved3_2 0x0 0
DTCM size 0x3 3 [4K]
Reserved4_10 0x0 0
Control 0x0005107D
Protect enable 0x1 1
Reserved0_1 0x0 0
Dcache enable 0x1 1
Reserved1_4 0xF 15
Big endian 0x0 0
Reserved2_4 0x0 0
Icache enable 0x1 1
Alt vector 0x0 0
Cache RRR 0x0 0
Disble load TBIT 0x0 0
DTCM enable 0x1 1
DTCM mode 0x0 0
ITCM enable 0x1 1
ITCM mode 0x0 0
Reserved3_12 0x0 0
Protection Region 0 0x0000003F
Enable 0x1 1
Size 0x1F 31 [4G]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 1 0x0000003B
Enable 0x1 1
Size 0x1D 29 [1G]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 2 0xF8000035
Enable 0x1 1
Size 0x1A 26 [128M]
Undef0_7 0x0 0
Base 0x7C000 507904 [0xF8000000]
Protection Region 3 0xC0000039
Enable 0x1 1
Size 0x1C 28 [512M]
Undef0_7 0x0 0
Base 0x60000 393216 [0xC0000000]
Protection Region 4 0xFF80002D
Enable 0x1 1
Size 0x16 22 [8M]
Undef0_7 0x0 0
Base 0x7FC00 523264 [0xFF800000]
Protection Region 5 0x00000037
Enable 0x1 1
Size 0x1B 27 [256M]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 6 0x00000000
Enable 0x0 0
Size 0x0 0 [invalid]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 7 0x00000000
Enable 0x0 0
Size 0x0 0 [invalid]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Region data perms 0x00333333
Region 0 0x3 3 [P:RW U:RW]
Region 1 0x3 3 [P:RW U:RW]
Region 2 0x3 3 [P:RW U:RW]
Region 3 0x3 3 [P:RW U:RW]
Region 4 0x3 3 [P:RW U:RW]
Region 5 0x3 3 [P:RW U:RW]
Region 6 0x0 0 [P:-- U:--]
Region 7 0x0 0 [P:-- U:--]
Region inst perms 0x00333333
Region 0 0x3 3 [P:RW U:RW]
Region 1 0x3 3 [P:RW U:RW]
Region 2 0x3 3 [P:RW U:RW]
Region 3 0x3 3 [P:RW U:RW]
Region 4 0x3 3 [P:RW U:RW]
Region 5 0x3 3 [P:RW U:RW]
Region 6 0x0 0 [P:-- U:--]
Region 7 0x0 0 [P:-- U:--]
DCache cfg 0x00000030
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x0 0
Region 3 0x0 0
Region 4 0x1 1
Region 5 0x1 1
Region 6 0x0 0
Region 7 0x0 0
ICache cfg 0x00000030
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x0 0
Region 3 0x0 0
Region 4 0x1 1
Region 5 0x1 1
Region 6 0x0 0
Region 7 0x0 0
Write buffer 0x00000030
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x0 0
Region 3 0x0 0
Region 4 0x1 1
Region 5 0x1 1
Region 6 0x0 0
Region 7 0x0 0
DTCM cfg 0x40000006
Reserved0_1 0x0 0
Size 0x3 3 [4K]
Undef0_7 0x0 0
Base 0x20000 131072 [0x40000000]
ITCM cfg 0x00000006
Reserved0_1 0x0 0
Size 0x3 3 [4K]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
- card_bootflags 101f34
- boot_read/write_sector 108350 108354
- Patching 10281C from e3510001 to e3510000
- 1027DC Card low-level init => F4240
- 101E18 Card init => 0
- Patching 101E28 from e3510001 to e3510000
- 101E18 Card init #2 => 1
- Saving RESCUE.LOG ...
Canon 5DC to compare with other vxworks cameras:
Magic Lantern Rescue
----------------------------
- Model ID: 0x0 ERROR
- Camera model: ???
- Firmware version: ??? / ???
- IMG naming: 100?????/????0000.JPG
- User PS: ??? ??? ???
- Boot flags: FIR=0 BOOT=-1 RAM=-1 UPD=-1
- ROMBASEADDR: 0xFF810000
CHDK CPU info for 0x0 ERROR
------------------------------
ID 0x41059461
Revision 0x1 1
Part 0x946 2374
ARM Arch 0x5 5
Variant 0x0 0
Implementor 0x41 65
Cache type 0x0F112112
Icache words/line 0x2 2 [8]
Icache absent 0x0 0
Icache assoc 0x2 2
Icache size 0x4 4 [8K]
Reserved0_2 0x0 0
Dcache words/line 0x2 2 [8]
Dcache absent 0x0 0
Dcache assoc 0x2 2
Dcache size 0x4 4 [8K]
Reserved1_2 0x0 0
Harvard/unified 0x1 1
Cache type 0x7 7
Reserved2_3 0x0 0
TCM type 0x000C00C0
Reserved0_2 0x0 0
ITCM absent 0x0 0
Reserved1_3 0x0 0
ITCM size 0x3 3 [4K]
Reserved2_4 0x0 0
DTCM absent 0x0 0
Reserved3_2 0x0 0
DTCM size 0x3 3 [4K]
Reserved4_10 0x0 0
Control 0x0005107D
Protect enable 0x1 1
Reserved0_1 0x0 0
Dcache enable 0x1 1
Reserved1_4 0xF 15
Big endian 0x0 0
Reserved2_4 0x0 0
Icache enable 0x1 1
Alt vector 0x0 0
Cache RRR 0x0 0
Disble load TBIT 0x0 0
DTCM enable 0x1 1
DTCM mode 0x0 0
ITCM enable 0x1 1
ITCM mode 0x0 0
Reserved3_12 0x0 0
Protection Region 0 0x0000003F
Enable 0x1 1
Size 0x1F 31 [4G]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 1 0x0000003B
Enable 0x1 1
Size 0x1D 29 [1G]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 2 0xF8000035
Enable 0x1 1
Size 0x1A 26 [128M]
Undef0_7 0x0 0
Base 0x7C000 507904 [0xF8000000]
Protection Region 3 0xC0000039
Enable 0x1 1
Size 0x1C 28 [512M]
Undef0_7 0x0 0
Base 0x60000 393216 [0xC0000000]
Protection Region 4 0xFF80002D
Enable 0x1 1
Size 0x16 22 [8M]
Undef0_7 0x0 0
Base 0x7FC00 523264 [0xFF800000]
Protection Region 5 0x00000035
Enable 0x1 1
Size 0x1A 26 [128M]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 6 0x00000000
Enable 0x0 0
Size 0x0 0 [invalid]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Protection Region 7 0x00000000
Enable 0x0 0
Size 0x0 0 [invalid]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
Region data perms 0x00333333
Region 0 0x3 3 [P:RW U:RW]
Region 1 0x3 3 [P:RW U:RW]
Region 2 0x3 3 [P:RW U:RW]
Region 3 0x3 3 [P:RW U:RW]
Region 4 0x3 3 [P:RW U:RW]
Region 5 0x3 3 [P:RW U:RW]
Region 6 0x0 0 [P:-- U:--]
Region 7 0x0 0 [P:-- U:--]
Region inst perms 0x00333333
Region 0 0x3 3 [P:RW U:RW]
Region 1 0x3 3 [P:RW U:RW]
Region 2 0x3 3 [P:RW U:RW]
Region 3 0x3 3 [P:RW U:RW]
Region 4 0x3 3 [P:RW U:RW]
Region 5 0x3 3 [P:RW U:RW]
Region 6 0x0 0 [P:-- U:--]
Region 7 0x0 0 [P:-- U:--]
DCache cfg 0x00000030
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x0 0
Region 3 0x0 0
Region 4 0x1 1
Region 5 0x1 1
Region 6 0x0 0
Region 7 0x0 0
ICache cfg 0x00000030
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x0 0
Region 3 0x0 0
Region 4 0x1 1
Region 5 0x1 1
Region 6 0x0 0
Region 7 0x0 0
Write buffer 0x00000030
Region 0 0x0 0
Region 1 0x0 0
Region 2 0x0 0
Region 3 0x0 0
Region 4 0x1 1
Region 5 0x1 1
Region 6 0x0 0
Region 7 0x0 0
DTCM cfg 0x40000006
Reserved0_1 0x0 0
Size 0x3 3 [4K]
Undef0_7 0x0 0
Base 0x20000 131072 [0x40000000]
ITCM cfg 0x00000006
Reserved0_1 0x0 0
Size 0x3 3 [4K]
Undef0_7 0x0 0
Base 0x0 0 [0x00000000]
- card_bootflags 101c14
- boot_read/write_sector 107d78 107d80
- 102424: cf_dir (cfata_init error)\n
- 1020a8: cf_read_dma (cfata_init error)\n
- 107C74 Card init => 0
- Saving RESCUE.LOG ...
Canon R6:
ID 0x414FC091
Revision 0x1 1
Part 0xC09 3081
ARM Arch 0xF 15
Variant 0x4 4
Implementor 0x41 65
Cache type 0x83338003
Icache min words/line 0x3 3 [8]
(zero) 0x0 0
L1 Icache policy 0x2 2
Dcache min words/line 0x3 3 [8]
Exclusives Reservation Granule 0x3 3 [8]
Cache Writeback Granule 0x3 3 [8]
(zero) 0x0 0
(register format) 0x4 4
TCM type 0x00000000
(raw value) 0x0 0
TLB type 0x00000404
TLB 0x0 0 [Unified TLB]
TLB entries 0x2 2 [256]
- 0x0 0
Lockable unified or data entries 0x4 4
Lockable instruction entries 0x0 0
(zero) 0x0 0
TTBCR 0x00000007
N 0x7 7 [TTBR0 table size 128 bytes]
(zero) 0x0 0
TTBR0 walks disabled 0x0 0
TTBR1 walks disabled 0x0 0
(zero) 0x0 0
Long descriptors 0x0 0
TTBR0 0xDFFC4800
IRGN[1] 0x0 0
Shareable 0x0 0
(impl. defined) 0x0 0
RGN (Outer cacheability) 0x0 0
NOS (Inner shareable) 0x0 0
IRGN[0] 0x0 0
Table address 0x1BFF890 29358224 [0xdffc4800]
TTBR1 0xDFFC0000
IRGN[1] 0x0 0
Shareable 0x0 0
(impl. defined) 0x0 0
RGN (Outer cacheability) 0x0 0
NOS (Inner shareable) 0x0 0
IRGN[0] 0x0 0
Table address 0x1BFF800 29358080 [0xdffc0000]
Multiprocessor ID 0x80000000
(raw value) 0x80000000 -2147483648
Revision ID 0x00000000
(raw value) 0x0 0
Processor feature 0 0x00001231
ARM inst set 0x1 1
Thumb inst set 0x3 3
Jazelle inst set 0x2 2
ThumbEE inst set 0x1 1
- 0x0 0
Processor feature 1 0x00000011
Programmers' model 0x1 1
Security extensions 0x1 1
Microcontr. prog model 0x0 0
Virt. extensions 0x0 0
Generic timer ext. 0x0 0
- 0x0 0
Debug feature 0x00010444
Coproc. dbg model 0x4 4
Coproc. secure dbg model 0x4 4
Memory-mapped dbg model 0x4 4
Coproc. trace model 0x0 0
Memory-mapped trace model 0x1 1
Debug model M 0x0 0
Perf. monitors 0x0 0
- 0x0 0
Aux feature 0x00000000
(raw value) 0x0 0
Mem model feature 0 0x00100103
VMSA support 0x3 3
PMSA support 0x0 0
Cache coherence 0x1 1
Outer shareable 0x0 0
TCM support 0x0 0
Auxiliary registers 0x1 1
FCSE support 0x0 0
- 0x0 0
Mem model feature 1 0x20000000
L1 Harvard cache VA 0x0 0
L1 unified cache VA 0x0 0
L1 Harvard cache s/w 0x0 0
L1 unified cache s/w 0x0 0
L1 Harvard cache 0x0 0
L1 unified cache 0x0 0
L1 cache test & clean 0x0 0
Branch predictor 0x2 2
Mem model feature 2 0x01230000
L1 Harvard fg prefetch 0x0 0
L1 Harvard bg prefetch 0x0 0
L1 Harvard range 0x0 0
Harvard TLB 0x0 0
Unified TLB 0x3 3
Mem barrier 0x2 2
WFI stall 0x1 1
HW access flag 0x0 0
Mem model feature 3 0x00102111
Cache maintain MVA 0x1 1 [Supported]
Cache maintain set/way 0x1 1 [Supported]
Branch predictor maintenance 0x1 1 [Invalidate all]
Maintenance broadcast 0x2 2
- 0x0 0
Transl. table coherent walk 0x1 1
Cached memory size 0x0 0 [4 GByte]
Supersection support 0x0 0 [Supported]
ISA feature 0 0x00101111
Swap instrs 0x1 1
Bitcount instrs 0x1 1
Bitfield instrs 0x1 1
CmpBranch instrs 0x1 1
Coproc instrs 0x0 0
Debug instrs 0x1 1
Divide instrs 0x0 0
- 0x0 0
ISA feature 1 0x13112111
Endian instrs 0x1 1
Exception instrs 0x1 1
Exception AR instrs 0x1 1
Extend instrs 0x2 2
IfThen instrs 0x1 1
Immediate instrs 0x1 1
Interwork instrs 0x3 3
Jazelle instrs 0x1 1
ISA feature 2 0x21232041
LoadStore instrs 0x1 1
Memhint instrs 0x4 4
MultiAccess Interruptible instructions 0x0 0
Mult instrs 0x2 2
MultS instrs 0x3 3
MultU instrs 0x2 2
PSR AR instrs 0x1 1
Reversal instrs 0x2 2
ISA feature 3 0x11112131
Saturate instrs 0x1 1
SIMD instrs 0x3 3
SVC instrs 0x1 1
SynchPrim instrs 0x2 2
TabBranch instrs 0x1 1
ThumbCopy instrs 0x1 1
TrueNOP instrs 0x1 1
T2 Exec Env instrs 0x1 1
ISA feature 4 0x00011142
Unprivileged instrs 0x2 2
WithShifts instrs 0x4 4
Writeback instrs 0x1 1
SMC instrs 0x1 1
Barrier instrs 0x1 1
SynchPrim_instrs_frac 0x0 0
PSR_M instrs 0x0 0
- 0x0 0
ISA feature 5 0x00000000
- 0x0 0
Cache level ID 0x09200003
Cache type, level1 0x3 3 [Separate Icache, Dcache]
Cache type, level2 0x0 0 [no cache]
Cache type, level3 0x0 0 [no cache]
Cache type, level4 0x0 0 [no cache]
Cache type, level5 0x0 0 [no cache]
Cache type, level6 0x0 0 [no cache]
Cache type, level7 0x0 0 [no cache]
Level of unification Inner Shareable 0x1 1
Level of coherency 0x1 1
Level of unification 0x1 1
(zero) 0x0 0
Cache size ID reg (data, level0) 0x700FE019
Line size in words 0x1 1 [8]
Associativity 0x3 3 [4]
Number of sets 0x7F 127 [128]
Write allocation 0x1 1
Read allocation 0x1 1
Write back 0x1 1
Write through 0x0 0
Cache size ID reg (inst, level0) 0x201FE019
Line size in words 0x1 1 [8]
Associativity 0x3 3 [4]
Number of sets 0xFF 255 [256]
Write allocation 0x0 0
Read allocation 0x1 1
Write back 0x0 0
Write through 0x0 0
SCTLR 0x40C5187D
MMU Enable 0x1 1
Strict Align 0x0 0
Data or Unified Cache Enable 0x1 1
CP15 Barrier Enable 0x1 1
- (SBO) 0x7 7
- (SBZ) 0x0 0
SWP/SWPB Enable 0x0 0
Branch Pred Enable 0x1 1
ICache Enable 0x1 1
High Vector 0x0 0
Round Robin 0x0 0
- (SBZ) 0x0 0
- (SBO) 0x1 1
HA flag 0x0 0
- (SBO) 0x1 1
WXN (virt. ext. only) 0x0 0
UWXN (virt. ext. only) 0x0 0
FIQ Enable 0x0 0
- (SBO) 0x3 3
VE 0x0 0
CPSR E 0x0 0
- (SBZ) 0x0 0
NMFI 0x0 0
TRE 0x0 0
AFE 0x0 0
Thumb exceptions 0x1 1
- (SBZ) 0x0 0
ACTLR 0x00000045
Cache & TLB maint. broadcast 0x1 1
L2 prefetch enable 0x0 0
L1 prefetch enable 0x1 1
Write full line of zeroes 0x0 0
(zero) 0x0 0
SMP 0x1 1
Exclusive cache 0x0 0
Alloc in one way 0x0 0
Parity on 0x0 0
- 0x0 0
ACTLR2 0x00000701
(raw value) 0x701 1793
CPACR 0xC0000000
(zero) 0x0 0
CP10 access permission 0x0 0
CP11 access permission 0x0 0
(zero) 0x0 0
D32DIS 0x1 1
ASEDIS 0x1 1
DACR 0x0000C000
(raw value) 0xC000 49152
NSACR (sec. ext. only) 0x55555555
(raw value) 0x55555555 1431655765
DBGDIDR 0x35137041
Revision 0x1 1
Variant 0x4 4
- (RAZ) 0x70 112
Version 0x3 3 [v7 full]
Context 0x1 1 [2]
BRP 0x5 5 [6]
WRP 0x3 3 [4]
DBGDRAR 0x00000000
Valid 0x0 0
- (UNK) 0x0 0
Address 0x0 0 [0x00000000]
DBGDSAR 0x00030000
Valid 0x0 0
- (UNK) 0x0 0
Address 0x30 48 [0x00030000]
DBGDSCR 0x03008002
HALTED 0x0 0
RESTARTED 0x1 1
MOE 0x0 0
SDABORT_l 0x0 0
ADABORT_l 0x0 0
UND_l 0x0 0
FS 0x0 0
DBGack 0x0 0
INTdis 0x0 0
UDCCdis 0x0 0
ITRen 0x0 0
HDBGen 0x0 0
MDBGen 0x1 1
SPIDdis 0x0 0
SPNIDdis 0x0 0
NS 0x0 0
ADAdiscard 0x0 0
ExtDCCmode 0x0 0
- (SBZ) 0x0 0
InstrCompl_l 0x1 1
PipeAdv 0x1 1
TXfull_l 0x0 0
RXfull_l 0x0 0
- (SBZ) 0x0 0
TXfull 0x0 0
RXfull 0x0 0
- (SBZ) 0x0 0
Config base addr reg 0xC1000000
(raw value) 0xC1000000 -1056964608
PLEIDR 0x00000000
(raw value) 0x0 0
TLB lockdown reg 0x00000000
(raw value) 0x0 0
PRRR 0x00098AA4
(raw value) 0x98AA4 625316
NMRR 0x44E048E0
(raw value) 0x44E048E0 1155549408
Canon RP:
ID 0x414FC091
Revision 0x1 1
Part 0xC09 3081
ARM Arch 0xF 15
Variant 0x4 4
Implementor 0x41 65
Cache type 0x83338003
Icache min words/line 0x3 3 [8]
(zero) 0x0 0
L1 Icache policy 0x2 2
Dcache min words/line 0x3 3 [8]
Exclusives Reservation Granule 0x3 3 [8]
Cache Writeback Granule 0x3 3 [8]
(zero) 0x0 0
(register format) 0x4 4
TCM type 0x00000000
(raw value) 0x0 0
TLB type 0x00000404
TLB 0x0 0 [Unified TLB]
TLB entries 0x2 2 [256]
- 0x0 0
Lockable unified or data entries 0x4 4
Lockable instruction entries 0x0 0
(zero) 0x0 0
TTBCR 0x00000007
N 0x7 7 [TTBR0 table size 128 bytes]
(zero) 0x0 0
TTBR0 walks disabled 0x0 0
TTBR1 walks disabled 0x0 0
(zero) 0x0 0
Long descriptors 0x0 0
TTBR0 0xE0004800
IRGN[1] 0x0 0
Shareable 0x0 0
(impl. defined) 0x0 0
RGN (Outer cacheability) 0x0 0
NOS (Inner shareable) 0x0 0
IRGN[0] 0x0 0
Table address 0x1C00090 29360272 [0xe0004800]
TTBR1 0xE0000000
IRGN[1] 0x0 0
Shareable 0x0 0
(impl. defined) 0x0 0
RGN (Outer cacheability) 0x0 0
NOS (Inner shareable) 0x0 0
IRGN[0] 0x0 0
Table address 0x1C00000 29360128 [0xe0000000]
Multiprocessor ID 0x80000000
(raw value) 0x80000000 -2147483648
Revision ID 0x00000000
(raw value) 0x0 0
Processor feature 0 0x00001231
ARM inst set 0x1 1
Thumb inst set 0x3 3
Jazelle inst set 0x2 2
ThumbEE inst set 0x1 1
- 0x0 0
Processor feature 1 0x00000011
Programmers' model 0x1 1
Security extensions 0x1 1
Microcontr. prog model 0x0 0
Virt. extensions 0x0 0
Generic timer ext. 0x0 0
- 0x0 0
Debug feature 0x00010444
Coproc. dbg model 0x4 4
Coproc. secure dbg model 0x4 4
Memory-mapped dbg model 0x4 4
Coproc. trace model 0x0 0
Memory-mapped trace model 0x1 1
Debug model M 0x0 0
Perf. monitors 0x0 0
- 0x0 0
Aux feature 0x00000000
(raw value) 0x0 0
Mem model feature 0 0x00100103
VMSA support 0x3 3
PMSA support 0x0 0
Cache coherence 0x1 1
Outer shareable 0x0 0
TCM support 0x0 0
Auxiliary registers 0x1 1
FCSE support 0x0 0
- 0x0 0
Mem model feature 1 0x20000000
L1 Harvard cache VA 0x0 0
L1 unified cache VA 0x0 0
L1 Harvard cache s/w 0x0 0
L1 unified cache s/w 0x0 0
L1 Harvard cache 0x0 0
L1 unified cache 0x0 0
L1 cache test & clean 0x0 0
Branch predictor 0x2 2
Mem model feature 2 0x01230000
L1 Harvard fg prefetch 0x0 0
L1 Harvard bg prefetch 0x0 0
L1 Harvard range 0x0 0
Harvard TLB 0x0 0
Unified TLB 0x3 3
Mem barrier 0x2 2
WFI stall 0x1 1
HW access flag 0x0 0
Mem model feature 3 0x00102111
Cache maintain MVA 0x1 1 [Supported]
Cache maintain set/way 0x1 1 [Supported]
Branch predictor maintenance 0x1 1 [Invalidate all]
Maintenance broadcast 0x2 2
- 0x0 0
Transl. table coherent walk 0x1 1
Cached memory size 0x0 0 [4 GByte]
Supersection support 0x0 0 [Supported]
ISA feature 0 0x00101111
Swap instrs 0x1 1
Bitcount instrs 0x1 1
Bitfield instrs 0x1 1
CmpBranch instrs 0x1 1
Coproc instrs 0x0 0
Debug instrs 0x1 1
Divide instrs 0x0 0
- 0x0 0
ISA feature 1 0x13112111
Endian instrs 0x1 1
Exception instrs 0x1 1
Exception AR instrs 0x1 1
Extend instrs 0x2 2
IfThen instrs 0x1 1
Immediate instrs 0x1 1
Interwork instrs 0x3 3
Jazelle instrs 0x1 1
ISA feature 2 0x21232041
LoadStore instrs 0x1 1
Memhint instrs 0x4 4
MultiAccess Interruptible instructions 0x0 0
Mult instrs 0x2 2
MultS instrs 0x3 3
MultU instrs 0x2 2
PSR AR instrs 0x1 1
Reversal instrs 0x2 2
ISA feature 3 0x11112131
Saturate instrs 0x1 1
SIMD instrs 0x3 3
SVC instrs 0x1 1
SynchPrim instrs 0x2 2
TabBranch instrs 0x1 1
ThumbCopy instrs 0x1 1
TrueNOP instrs 0x1 1
T2 Exec Env instrs 0x1 1
ISA feature 4 0x00011142
Unprivileged instrs 0x2 2
WithShifts instrs 0x4 4
Writeback instrs 0x1 1
SMC instrs 0x1 1
Barrier instrs 0x1 1
SynchPrim_instrs_frac 0x0 0
PSR_M instrs 0x0 0
- 0x0 0
ISA feature 5 0x00000000
- 0x0 0
Cache level ID 0x09200003
Cache type, level1 0x3 3 [Separate Icache, Dcache]
Cache type, level2 0x0 0 [no cache]
Cache type, level3 0x0 0 [no cache]
Cache type, level4 0x0 0 [no cache]
Cache type, level5 0x0 0 [no cache]
Cache type, level6 0x0 0 [no cache]
Cache type, level7 0x0 0 [no cache]
Level of unification Inner Shareable 0x1 1
Level of coherency 0x1 1
Level of unification 0x1 1
(zero) 0x0 0
Cache size ID reg (data, level0) 0x700FE019
Line size in words 0x1 1 [8]
Associativity 0x3 3 [4]
Number of sets 0x7F 127 [128]
Write allocation 0x1 1
Read allocation 0x1 1
Write back 0x1 1
Write through 0x0 0
Cache size ID reg (inst, level0) 0x200FE019
Line size in words 0x1 1 [8]
Associativity 0x3 3 [4]
Number of sets 0x7F 127 [128]
Write allocation 0x0 0
Read allocation 0x1 1
Write back 0x0 0
Write through 0x0 0
SCTLR 0x40C5187D
MMU Enable 0x1 1
Strict Align 0x0 0
Data or Unified Cache Enable 0x1 1
CP15 Barrier Enable 0x1 1
- (SBO) 0x7 7
- (SBZ) 0x0 0
SWP/SWPB Enable 0x0 0
Branch Pred Enable 0x1 1
ICache Enable 0x1 1
High Vector 0x0 0
Round Robin 0x0 0
- (SBZ) 0x0 0
- (SBO) 0x1 1
HA flag 0x0 0
- (SBO) 0x1 1
WXN (virt. ext. only) 0x0 0
UWXN (virt. ext. only) 0x0 0
FIQ Enable 0x0 0
- (SBO) 0x3 3
VE 0x0 0
CPSR E 0x0 0
- (SBZ) 0x0 0
NMFI 0x0 0
TRE 0x0 0
AFE 0x0 0
Thumb exceptions 0x1 1
- (SBZ) 0x0 0
ACTLR 0x00000045
Cache & TLB maint. broadcast 0x1 1
L2 prefetch enable 0x0 0
L1 prefetch enable 0x1 1
Write full line of zeroes 0x0 0
(zero) 0x0 0
SMP 0x1 1
Exclusive cache 0x0 0
Alloc in one way 0x0 0
Parity on 0x0 0
- 0x0 0
ACTLR2 0x00000701
(raw value) 0x701 1793
CPACR 0xC0000000
(zero) 0x0 0
CP10 access permission 0x0 0
CP11 access permission 0x0 0
(zero) 0x0 0
D32DIS 0x1 1
ASEDIS 0x1 1
DACR 0x0000C000
(raw value) 0xC000 49152
NSACR (sec. ext. only) 0x55555555
(raw value) 0x55555555 1431655765
DBGDIDR 0x35137041
Revision 0x1 1
Variant 0x4 4
- (RAZ) 0x70 112
Version 0x3 3 [v7 full]
Context 0x1 1 [2]
BRP 0x5 5 [6]
WRP 0x3 3 [4]
DBGDRAR 0x00000000
Valid 0x0 0
- (UNK) 0x0 0
Address 0x0 0 [0x00000000]
DBGDSAR 0x00030000
Valid 0x0 0
- (UNK) 0x0 0
Address 0x30 48 [0x00030000]
DBGDSCR 0x03000002
HALTED 0x0 0
RESTARTED 0x1 1
MOE 0x0 0
SDABORT_l 0x0 0
ADABORT_l 0x0 0
UND_l 0x0 0
FS 0x0 0
DBGack 0x0 0
INTdis 0x0 0
UDCCdis 0x0 0
ITRen 0x0 0
HDBGen 0x0 0
MDBGen 0x0 0
SPIDdis 0x0 0
SPNIDdis 0x0 0
NS 0x0 0
ADAdiscard 0x0 0
ExtDCCmode 0x0 0
- (SBZ) 0x0 0
InstrCompl_l 0x1 1
PipeAdv 0x1 1
TXfull_l 0x0 0
RXfull_l 0x0 0
- (SBZ) 0x0 0
TXfull 0x0 0
RXfull 0x0 0
- (SBZ) 0x0 0
Config base addr reg 0xC1000000
(raw value) 0xC1000000 -1056964608
PLEIDR 0x00000000
(raw value) 0x0 0
TLB lockdown reg 0x00000000
(raw value) 0x0 0
PRRR 0x00098AA4
(raw value) 0x98AA4 625316
NMRR 0x44E048E0
(raw value) 0x44E048E0 1155549408