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Messages - atonal

Pages: [1]
1
A few extra registers that (at least) 7D2 now prints:

Code: [Select]
Multiprocessor ID   0x00000000
SCTLR   0x08E5187D
    (raw value)             0x8E5187D 149231741
ACTLR   0x00000020
    (raw value)             0x20 32
ACTLR2  0x00000000
    (raw value)             0x0 0
CPACR   0x00000000
    (raw value)             0x0 0

2
I did the 7D2. Might contain typos and other mistakes, my screen shots weren't all crystal clear. I can upload the pics somewhere if someone wants to double check any of the data.

Code: [Select]
---------------------------------------------- page 1
CHDK CPU info for 0x289 7D2
-----------------------------
ID              0x411FC143
    Revision                0x3 3
    Part                    0xC14 3092
    ARM Arch                0xF 15
    Variant                 0x1 1
    Implementor             0x41 65
Cache type      0x8003C003
    Icache min words/line   0x3 3 [8]
    (zero)                  0x0 0
    L1 Icache policy        0x3 3
    Dcache min words/line   0x3 3 [8]
    Exclusives Reservation Granule  0x0 0 [no info]
    Cache Writeback Granule 0x0 0 [no info]
    (zero)                  0x0 0
    (register format)       0x4 4
TCM type        0x00010001
    (raw value)             0x10001 65537
MPU type        0x00000800
    S                       0x0 0
    -                       0x0 0
    Num of MPU regions      0x8 8
Processor feature 0 0x00000131
    ARM inst set            0x1 1
    Thumb inst set          0x3 3
    Jazelle inst set        0x1 1
    ThumbEE inst set        0x0 0
    -                       0x0 0
Processor feature 1 0x00000001
    Programmers' model      0x1 1
    Security extensions     0x0 0
    Microcontr, prog model  0x0 0
    -                       0x0 0
Debug feature   0x00010400
    (raw value)             0x10400 66560
Aux feature     0x00000000
    (raw value)             0x0 0
Mem model feature 0 0x00210030
    VMSA support            0x0 0
    PMSA support            0x3 3
    Cache coherence         0x0 0
    Outer shareable         0x0 0
    TCM support             0x1 1
    Auxiliary registers     0x2 2
---------------------------------------------- page 2
    FCSE support            0x0 0
    -                       0x0 0
Mem model feature 1 0x00000000
    L1 Harvard cache VA     0x0 0
    L1 unified cache VA     0x0 0
    L1 Harvard cache s/w    0x0 0
    L1 unified caceh s/w    0x0 0
    L1 Harvard cache        0x0 0
    L1 unified cache        0x0 0
    L1 cache test & clean   0x0 0
    Branch predictor        0x0 0
Mem model feature 2 0x01200000
    L1 Harvard fg prefetch  0x0 0
    L1 Harvard bg prefetch  0x0 0
    Harvar TLB              0x0 0
    Unified TLB             0x0 0
    Mem barrier             0x2 2
    WFI stall               0x1 1
    HW access flag          0x0 0
Mem model feature 3 0x00000011
    Cache maintain MVA      0x1 1
    Cache maintain s/w      0x1 1
    BP maintain             0x0 0
    -                       0x0 0
    Supersection support    0x0 0
ISA feature 0 0x01101111
    Swap instrs             0x1 1
    Bitcount instrs         0x1 1
    Bitfield instrs         0x1 1
    CmpBranch instrs        0x1 1
    Coproc instrs           0x0 0
    Debug instrs            0x1 1
    Divide instrs           0x1 1
    -                       0x0 0
ISA feature 1 0x13112111
    Endian instrs           0x1 1
    Exception instrs        0x1 1
    Exception AR instrs     0x1 1
    Extend instrs           0x2 2
    IfThen instrs           0x1 1
    Immediate instrs        0x1 1
    Interwork instrs        0x3 3
    Jazelle instrs          0x1 1
ISA feature 2 0x21232131
    LoadStore instrs        0x1 1
    Memhint instrs          0x3 3
---------------------------------------------- page 3
    MultiAccess Interruptible instructions 0x1 1
    Mult instrs             0x2 2
    MultS instrs            0x3 3
    MultU instrs            0x2 2
    PSR AR instrs           0x1 1
    Reversal instrs         0x2 2
ISA feature 3 0x01112131
    Saturate instrs         0x1 1
    SIMD instrs             0x3 3
    SVC instrs              0x1 1
    SynchPrim instrs        0x2 2
    TabBranch instrs        0x1 1
    ThumbCopy instrs        0x1 1
    TrueNOP instrs          0x1 1
    T2 Exec Env instrs      0x0 0
ISA feature 4 0x00010142
    Unprivileged instrs     0x2 2
    WithShifts instrs       0x4 4
    Writeback instrs        0x1 1
    SMC instrs              0x0 0
    Barrier instrs          0x1 1
    SynchPrim_instrs_frac   0x0 0
    PSR_M instrs            0x0 0
    -                       0x0 0
ISA feature 5 0x00000000
    -                       0x0 0
Cache level ID 0x09000003
    Cache type, level1      0x3 3 [Separate Icache, Dcache]
    Cache type, level2      0x0 0 [no cache]
    Cache type, level3      0x0 0 [no cache]
    Cache type, level4      0x0 0 [no cache]
    Cache type, level5      0x0 0 [no cache]
    Cache type, level6      0x0 0 [no cache]
    Cache type, level7      0x0 0 [no cache]
    Cache type, level8      0x0 0 [no cache]
    Level of coherency      0x1 1
    Level of unification    0x1 1
    (zero)                  0x0 0
Cache size ID reg (data, level0) 0xF00FE019
    Line size in words      0x1 1 [8]
    Associativity           0x3 3 [4]
    Number of sets          0x7F 127 [128]
    Write allocation        0x1 1
    Read allocation         0x1 1
    Write back              0x1 1
    Write through           0x1 1
Cache size ID reg (inst, level0) 0xF00FE019
---------------------------------------------- page 4
    Line size inf words     0x1 1 [8]
    Associativity           0x3 3 [4]
    Number of sets          0x7F 127 [128]
    Write allocation        0x1 1
    Read allocation         0x1 1
    Write back              0x1 1
    Write through           0x1 1
Build options 1 0x00010000
    (raw value)             0x10000 65536
Build options 2 0x00CFC010
    (raw value)             0xCFC010 13615120
ARCM region reg 0x00000015
    Enabled                 0x1 1
    -                       0x0 0
    Size                    0x5 5 [16K]
    -                       0x0 0
    Base address            0x0 0 [0x00000000]
BTCM region reg 0x0000001D
    Enabled                 0x1 1
    -                       0x0 0
    Size                    0x7 7 [64K]
    -                       0x0 0
    Base address            0x80000 524288 [0x80000000]
MPU region 0 base 0x00000000
    Base address            0x0 0
MPU region 0 size & enable  0x0000003F
    Enabled                 0x1 1
    Size                    0x1F 31 [4G]
    -                       0x0 0
    Sub-regions disabled    0x0 0 [00000000]
MPU region 0 access control 0x00000320
    Region attributes       0x20 32 [Inner Non-cacheable; Outer Non-cacheable; Non-shared]
    -                       0x0 0
    Access permission       0x3 3 [P:RW U:RW]
    -                       0x0 0
    Execute never           0x0 0
MPU region 1 base           0x00000000
    Base address            0x0 0
MPU region 1 size & enable  0x0000003B
    Enabled                 0x1 1
    Size                    0x1D 29 [1G]
    -                       0x0 0
    Sub-regions disabled    0x0 0 [00000000]
MPU region 1 access contro  0x00000329
    Region attributes       0x29 41 [Inner Write-back, write-allocat; Outer Write-back, write-allocate; Non-shared]
---------------------------------------------- page 5
    -                       0x0 0
    Access permission       0x3 3 [P:RW U:RW]
    -                       0x0 0
    Execute never           0x0 0
MPU region 2 base 0xBFE00000
    Base address            0xBFE00000 -1075838976
MPU region 2 size & enable  0x00000029
    Enabled                 0x1 1
    Size                    0x14 20 [2M]
    -                       0x0 0
    Sub-regions disabled    0x0 0 [00000000]
MPU region 2 access control 0x00000324
    Region attributes       0x24 36 [Inner Non-cacheable; Outer Non-cacheable; Shared]
    -                       0x0 0
    Access permission       0x3 3 [P:RW U:RW]
    -                       0x0 0
    Execute never           0x0 0
MPU region 3 base 0xC0000000
    Base address            0xC0000000 -1073741824
MPU region 3 size & enable  0x0000003B
    Enabled                 0x1 1
    Size                    0x1D 29 [1G]
    -                       0x0 0
    Sub-regions disabled    0x0 0 [00000000]
MPU region 3 access control 0x00000305
    Region attributes       0x5 5 [Shareable device; Shareble]
    -                       0x0 0
    Access permission       0x3 3 [P:RW U:RW]
    -                       0x0 0
    Execute never           0x0 0
MPU region 4 base 0xDFE00000
    Base address            0xDFE00000 -538968064
MPU region 4 size & enable  0x00000029
    Enabled                 0x1 1
    Size                    0x14 20 [2M]
    -                       0x0 0
    Sub-regions disabled    0x0 0 [00000000]
MPU region 4 access control 0x00000324
    Region attributes       0x24 36 [Inner Non-cacheable; Outer Non-cacheable; Shared]
    -                       0x0 0
    Access permission       0x3 3 [P:RW U:RW]
    -                       0x0 0
    Execute never           0x0 0
MPU region 5 base 0xEE000000
    Base address            0xEE000000 -301989888
MPU region 5 size & enable  0x00000031
    Enabled                 0x1 1
---------------------------------------------- page 6
    Size                    0x18 24 [32M]
    -                       0x0 0
    Sub-regions disabled    0x0 0 [00000000]
MPU region 5 access control 0x00000329
    Region attributes       0x29 41 [Inner Write-back, write-allocate; Outer Write-back, write-allocate; Non-shared]
    -                       0x0 0
    Access permission       0x3 3 [P:RW U:RW]
    -                       0x0 0
    Execute never           0x0 0
MPU region 6 base 0xFE000000
    Base address            0xFE000000 -33554432
MPU region 6 size & enable 0x00000031
    Enabled                 0x1 1
    Size                    0x18 24 [32M]
    -                       0x0 0
    Sub-regions disabled    0x0 0 [00000000]
MPU region 6 access control 0x00000329
    Region attributes       0x29 41 [Inner Write-back, write-allocate; Outer Write-back, write-allocate; Non-shared]
    -                       0x0 0
    Access permission       0x3 [P:RW U:RW]
    -                       0x0 0
    Execute never           0x0 0
MPU region 7 base 0x00000000
    Base address            0x0 0
MPU region 7 size & enable 0x00000000
    Enabled                 0x0 0
    Size                    0x0 0 [invalid]
    -                       0x0 0
    Sub-regions disabled    0x0 0 [00000000]
MPU region 7 access control 0x00000000
    Region attributes       0x0 0 [Strongly ordered, shareable; ]
    -                       0x0 0
    Access permission       0x0 0 [P:-- U:--]
    -                       0x0 0
    Execute never           0x0 0


3
Camera-specific discussion / Re: Canon 80D
« on: July 13, 2016, 07:48:31 PM »
Added my interpretation of the memory mapping to the wiki.

4
Camera-specific discussion / Re: Canon 7D Mark II
« on: June 18, 2016, 09:41:36 AM »
The LED blinks!

5
Camera-specific discussion / Re: Canon 7D Mark II
« on: June 16, 2016, 08:15:10 AM »
would you mind sending me a PM with the DUMMY7D2.FIR attachment

You can find the link to the FIR from a1ex's post:

I'm looking for a 7D2 user able and willing to measure the current from his camera while running this FIR.

6
Camera-specific discussion / Re: Canon 7D Mark II
« on: June 15, 2016, 06:49:57 PM »
Just to elaborate a bit on the trial with my camera: after trying to do the firmware update with the DUMMY7D2.FIR, the screen went black and the camera became totally unresponsive. Shutting down and removing the battery for a while made the camera come back to live again. Here's a short video, so you know what to expect: https://dl.dropboxusercontent.com/u/37493196/MOV_0017.mp4

Unfortunately I don't have an external power adapter nor a multimeter, so I can't help with this step.

7
Camera-specific discussion / Re: Canon 7D Mark II
« on: May 30, 2016, 08:59:52 PM »
I don't know what is .W at the end of B and BLX...

The .W forces a 32-bit instruction in Thumb-2 mode, even if a 16-bit instruction existed. [1]

I also tried to construct the macro for B.W, based on the ARMv7-M specification which defines the 32-bit B.W [2]. Here's what I came up with:

Code: [Select]
#define OFFSET(pc,dest) ((uint32_t)(dest) - (uint32_t)(pc) - 4)
#define S(offset) (((offset) >> 24) & 0x1)
#define I1(offset) (((offset) >> 23) & 0x1)
#define I2(offset) (((offset) >> 22) & 0x1)
#define IMM10(offset) (((offset) >> 12) & 0x3ff)
#define IMM11(offset) (((offset) >> 1) & 0x7ff)
#define J1(i1,s) ((!((i1) ^ (s))) & 0x1)
#define J2(i2,s) ((!((i2) ^ (s))) & 0x1)
 
#define B_W_INSTR(pc,dest) \
    ( \
      0xf0009000 | \
      (S(OFFSET(pc,dest)) << 26) | \
      (IMM10(OFFSET(pc,dest)) << 16) | \
      (J1(I1(OFFSET(pc,dest)),S(OFFSET(pc,dest))) << 13) | \
      (J2(I2(OFFSET(pc,dest)),S(OFFSET(pc,dest))) << 11) | \
      (IMM11(OFFSET(pc,dest))) \
    )

Not extensively tested, so feel free to fix and improve.

I guess the binutils implementation [3] could be used as a reference too.

For the BLX I did not find a specification that defines the .W version. If such a specification exists, I'd be glad to see it.

From the ARM page [1] I can see that there are two different BLX instructions: BLX <Rm>, and BLX <label>. The latter one seems to be the only one which has a 32-bit version. Is that the one you're after, a1ex? Although, both the ARM page and the ARMv7-M spec says that the BLX <label> is not part of ARMv7-M. Do we know for sure what architecture the DICIG 6 has?

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0489e/Cihfddaf.html
[2] https://web.eecs.umich.edu/~prabal/teaching/resources/eecs373/ARMv7-M_ARM.pdf
[3] https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob;f=gas/config/tc-arm.c;h=3b0a021a379bc72c21ba8f0c312789fc25dd2d5e;hb=HEAD#l22108

8
General Chat / Re: Canon EOS 70D (RAW possibility)
« on: April 23, 2014, 02:54:32 PM »
I was thinking of doing the port using a blog to track down every action I do, and having at least one follower doing the same things would help quite a bit

Is the blog happening? At least I'm interested in reading how the porting goes, and perhaps learn a thing or two about the ML internals too.

Pages: [1]